Digitally calibrated successive approximation register analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-9531400-B1
Application number	US-201514932798-A
Country	US
Kind code	B1
Filing date	Nov 4, 2015
Priority date	Nov 4, 2015
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

A circuit can include a voltage comparator V d having a first input, a second input, and an output; a first plurality of capacitors C p [0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the first input of the voltage comparator V d , wherein each top plate is also switchably electrically coupled with a common mode voltage V cm , and wherein each bottom plate is switchably electrically coupled between a first input voltage V inp , a reference voltage V ref , the common mode voltage V cm , and ground; a second plurality of capacitors C n [0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the second input of the voltage comparator V d , wherein each top plate is also switchably electrically coupled with the common mode voltage V cm , and wherein each bottom plate is switchably electrically coupled between a second input voltage V inn , the reference voltage V ref , the common mode voltage V cm , and ground; and a successive approximation register (SAR) controller coupled with the output of the voltage comparator V d .

First claim

What is claimed is:

1. A circuit, comprising:
a voltage comparator V d having a first input, a second input, and an output;
a first plurality of capacitors C p [0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the first input of the voltage comparator V d , wherein each top plate is also switchably electrically coupled with a common mode voltage V cm , and wherein each bottom plate is switchably electrically coupled between a first input voltage V inn , a reference voltage V ref , the common mode voltage V cm , and ground;
a second plurality of capacitors C n [0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the second input of the voltage comparator V d , wherein each top plate is also switchably electrically coupled with the common mode voltage V cm , and wherein each bottom plate is switchably electrically coupled between a second input voltage V inp , the reference voltage V ref , the common mode voltage V cm , and ground; and
a successive approximation register (SAR) controller coupled with the output of the voltage comparator V d , wherein the SAR controller is configured to implement a collapsible SAR algorithm that uses balanced ternary values (−1,0,+1) for each bit to encode an analog input.

2. The circuit of claim 1 , wherein the first plurality of capacitors C p [0:n] includes 8 capacitors C p [0:7].

3. The circuit of claim 2 , wherein the second plurality of capacitors C n [0:n] includes 8 capacitors C n [0:7].

4. The circuit of claim 3 , wherein the first and second pluralities of capacitors together represent two 4-bit sections C[0:7].

5. The circuit of claim 4 , wherein the two 4-bit sections include two most significant bits (MSBs) C[3] and C[7], each MSB having three corresponding least significant bits (LSBs) C[2:0] and C[6:4], respectively.

6. The circuit of claim 5 , wherein each bottom plate of the first plurality of capacitors is electrically coupled with the first input voltage V inp , each bottom plate of the second plurality of capacitors is electrically coupled with the second input voltage V inn , and each top plate of the first and second pluralities of capacitors is electrically coupled with the common mode voltage V cm during a sampling phase.

7. The circuit of claim 6 , wherein each top plate of the first and second pluralities of capacitors is disconnected from the common mode voltage V cm and each bottom plate of the first and second pluralities of capacitors is electrically coupled with the common mode voltage V cm during a first conversion cycle.

8. The circuit of claim 1 , wherein the common mode voltage V cm is equal to one-half of the reference voltage V ref .

9. A circuit, comprising:
a voltage comparator V d having a first input, a second input, and an output;
a first plurality of capacitors C p [0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the first input of the voltage comparator V d , wherein each top plate is also switchably electrically coupled with a common mode voltage V cm , and wherein each bottom plate is switchably electrically coupled between a first input voltage V inp , a reference voltage V ref , the common mode voltage V cm , and ground, wherein the first plurality of capacitors C p [0:n] includes 8 capacitors C p 0:7];
a second plurality of capacitors C n [0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the second input of the voltage comparator V d , wherein each top plate is also switchably electrically coupled with the common mode voltage V cm , and wherein each bottom plate is switchably electrically coupled between a second input voltage V inn , the reference voltage V ref , the common mode voltage V cm , and ground; wherein the second plurality of capacitors C n [0:n] includes 8 capacitors C n [0:7], wherein the first and second pluralities of capacitors together represent two 4-bit sections C[0:7], and wherein the two 4-bit sections include two most significant bits (MSBs) C[3] and C[7] , each MSB having three corresponding least significant bits (LSBs) C[2:0] and C[6:4], respectively; and
a successive approximation register (SAR) controller coupled with the output of the voltage comparator V d , wherein a bit weight of each of the most significant bits (MSBs) C[3] and C[7] is equal to a sum of bit weights of the corresponding least significant bits (LSBs) C[2]+C[1]+C[0] and C[6]+C[5]+C[4], respectively.

10. A circuit, comprising:
a voltage comparator V d having a first input, a second input, and an output;
a first plurality of capacitors C p [0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the first input of the voltage comparator V d , wherein each top plate is also switchably electrically coupled with a common mode voltage V cm , and wherein each bottom plate is switchably electrically coupled between a first input voltage V inp , a reference voltage V ref , the common mode voltage V cm , and ground, wherein the first plurality of capacitors C p [0:n] includes 8 capacitors C p [0:7];
a second plurality of capacitors C n [0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the second input of the voltage comparator V d , wherein each top plate is also switchably electrically coupled with the common mode voltage V cm , and wherein each bottom plate is switchably electrically coupled between a second input voltage V inn , the reference voltage V ref , the common mode voltage V cm , and ground, wherein the second plurality of capacitors C n [0:n] includes 8 capacitors C n [0:7], wherein the first and second pluralities of capacitors together represent two 4-bit sections C[0:7], and wherein the two 4-bit sections include two most significant bits (MSBs) C[3] and C[7], each MSB having three corresponding least significant bits (LSBs) C[2:0] and C[6:4], respectively; and
a successive approximation register (SAR) controller coupled with the output of the voltage comparator V d , wherein the SAR controller is configured to implement a collapsible SAR algorithm that performs a comparison of the conversion residue to the mid-code of the remaining least significant bits (LSBs).

11. The circuit of claim 10 , wherein the collapsible SAR algorithm determines the most significant bit (MSB) value of the remaining least significant bits (LSBs) based on the polarity of the comparison.

12. A circuit, comprising:
a voltage comparator V d having a first input, a second input, and an output;
a first plurality of capacitors C p [0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the first input of the voltage comparator V d , wherein each top plate is also switchably electrically coupled with a common mode voltage V cm , and wherein each bottom plate is switchably electrically coupled between a first input voltage V inp , a reference voltage V ref , the common mode voltage V cm , and ground;
a second plurality of capacitors C n [0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the second input of the voltage comparator V d , wherein each top plate is also switchably electrically coupled with the common mode voltage V cm , and wherein each bottom plate is switchably electrically coupled between a second input voltage V inn , the reference voltage V ref , the common mode voltage V cm , and ground; and
a successive approximation register (SAR) controller coupled with the output of the voltage compa

Assignees

• Avnera Corp

Inventors

• Wen Jianping
• Link Garry
• Lee Wai

Classifications

• H03M1/38

  sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14) · CPC title

• H03M1/0692 Primary

  using a diminished radix representation, e.g. radix 1.95 · CPC title

• H03M1/804

  with charge redistribution · CPC title

• H03M1/468

  in which the input S/H circuit is merged with the feedback DAC array · CPC title

• H03M1/0682

  using a differential network structure, i.e. symmetrical with respect to ground · CPC title