High speed illumination driver for tof applications

Patent metadata

Field	Value
Publication number	US-2016341819-A1
Application number	US-201514856205-A
Country	US
Kind code	A1
Filing date	Sep 16, 2015
Priority date	May 22, 2015
Publication date	Nov 24, 2016
Grant date	—

Abstract

The disclosure provides a circuit. The circuit includes an amplifier and a digital to analog converter (DAC). The amplifier receives a reference voltage at an input node of the amplifier. The DAC is coupled to the amplifier through a refresh switch. The DAC includes one or more current elements. Each current element of the one or more current elements receives a clock. The DAC includes one or more switches corresponding to the one or more current elements. A feedback switch is coupled between the one or more switches and a feedback node of the amplifier. The DAC provides a feedback voltage at the feedback node of the amplifier.

First claim

What is claimed is:

1 . A circuit comprising:
an amplifier configured to receive a reference voltage at an input node of the amplifier; and a digital to analog converter (DAC) coupled to the amplifier through a refresh switch, the DAC comprising:
one or more current elements, each current element of the one or more current elements configured to receive a clock;
one or more switches corresponding to the one or more current elements; and
a feedback switch coupled between the one or more switches and a feedback node of the amplifier, wherein the DAC is configured to provide a feedback voltage at the feedback node of the amplifier.

2 . The circuit of claim 1 further comprising an LED (light emitting diode) coupled between a primary power source and the DAC.

3 . The circuit of claim 1 , wherein the DAC receives a DAC input, the DAC input comprises one or more enable signals corresponding to the one or more current elements, wherein a current element of the one or more current elements is activated when a corresponding enable signal received by the current element is at logic high.

4 . The circuit of claim 1 , wherein each current element of the one or more current element comprises:
an AND gate configured to generate a control signal in response to a clock and an enable signal of the one or more enable signals; a first transistor configured to receive the control signal; a second transistor coupled to the first transistor and the refresh switch; and a resistor coupled to the second transistor at a primary node, wherein one end of the resistor is coupled to a secondary power source.

5 . The circuit of claim 4 , wherein the one or more enable signals is configured to activate the one or more switches.

6 . The circuit of claim 1 , wherein each switch of the one or more switches is coupled between the primary node and the feedback switch.

7 . The circuit of claim 6 , wherein a first switch of the one or more switches is activated when a first current element of the one or more current elements is activated, wherein the first switch corresponds to the first current element.

8 . The circuit of claim 1 operates in a feedback mode and a refresh mode, wherein in the feedback mode:
the feedback switch is activated;
the refresh switch is inactivated;
the clock is at logic high;
a set of current elements of the one or more current elements is activated based on the DAC input; and
a corresponding set of switches of the one or more switches is activated based the set of current elements activated, wherein the feedback voltage at the feedback node of the amplifier is measured from a current through the resistor in each current element of the set of current elements.

9 . The circuit of claim 1 , wherein in the refresh mode:
the feedback switch is inactivated; the refresh switch is activated; the clock is at logic low; and the amplifier is configured to generate an error voltage from the feedback voltage and the reference voltage, the error voltage is provided to a second transistor in each current element of the set of current elements.

10 . The circuit of claim 9 , wherein the error voltage is configured to change a current through each current element of the set of current elements in a subsequent feedback mode.

11 . A method comprising:
activating a set of current elements of one or more current elements based on a DAC input and when a clock is at logic high; activating a corresponding set of switches of a one or more switches based on the set of current elements activated; and measuring a feedback voltage from a current through a resistor in each current element of the set of current elements.

12 . The method of claim 11 further comprising:
inactivating the one or more current element when the clock is at logic low;
comparing the feedback voltage and a reference voltage to generate an error voltage;
providing the error voltage to each current element of the one or more current elements; and
activating the set of current elements of the one or more current elements when the clock is at logic high, wherein the error voltage is configured to change a current through each current element of the set of current elements.

13 . The method of claim 11 further comprising providing a current from a primary power source to each current element of the set of current elements.

14 . The method of claim 11 , wherein activating the set of current elements of the one or more current elements further comprises receiving the DAC input, the DAC input comprises one or more enable signals corresponding to the one or more current elements, wherein the one or more enable signals is configured to activate the one or more switches.

15 . The method of claim 11 , wherein each current element of the one or more current element comprises:
an AND gate configured to generate a control signal in response to the clock and an enable signal of the one or more enable signals; a first transistor configured to receive the control signal; a second transistor coupled to the first transistor; and a resistor coupled to the second transistor at a primary node, wherein one end of the resistor is coupled to a secondary power source.

16 . A time-of-flight (TOF) system comprising a circuit, the circuit configured to transmit light pulses, the circuit comprising:
an amplifier configured to receive a reference voltage at an input node of the amplifier; and a digital to analog converter (DAC) coupled to the amplifier through a refresh switch, the DAC comprising:
one or more current elements configured to receive a DAC input, each current element of the one or more current elements configured to receive a clock;
one or more switches corresponding to the one or more current elements; and
a feedback switch coupled between the one or more switches and a feedback node of the amplifier, wherein the DAC is configured to provide a feedback voltage at the feedback node of the amplifier.

17 . The TOF system of claim 16 further comprising:
a pixel array having a plurality of pixels configured to receive reflected light pulses, the transmitted light pulses are scattered by a target to generate the reflected light pulses;
an analog to digital converter (ADC) coupled to the pixel array and configured to convert an analog signal from each pixel of the plurality of pixels to a digital signal; and
a processor coupled to the ADC, and configured to process the digital signal.

18 . The TOF system of claim 16 , wherein the circuit further comprises an LED (light emitting diode) coupled between a primary power source and the DAC.

19 . The TOF system of claim 16 , wherein the circuit operates in a feedback mode and a refresh mode, wherein in the feedback mode:
the feedback switch is activated; the refresh switch is inactivated; the clock is at logic high; a set of current elements of the one or more current elements is activated based on the DAC input; and a corresponding set of switches of the one or more switches is activated based the set of current elements activated, wherein the feedback voltage at the feedback node of the amplifier is measured from a current through a resistor in each current element of the set of current elements.

20 . The TOF system of claim 16 , wherein in the refresh mode:
the feedback switch is inactivated; the refresh switch is activated; the clock is at logic low; and the amplifier is configured to generate an error voltage from the feedback voltage and the re

Assignees

• Texas Instruments Inc

Inventors

• Venkataraman Jagannathan

Classifications

• H03M1/0682

  using a differential network structure, i.e. symmetrical with respect to ground · CPC title

• G01S7/484 Primary

  Transmitters · CPC title

• H03M3/502

  Details of the final digital/analogue conversion following the digital delta-sigma modulation · CPC title

• H03M3/358

  of non-linear distortion, e.g. instability (avoiding instability by structural design H03M3/44) · CPC title

• G01S17/894

  Three-dimensional [3D] imaging with simultaneous measurement of time-of-flight at a two-dimensional [2D] array of receiver pixels, e.g. time-of-flight cameras or flash lidar · CPC title