Semiconductor packages and methods of packaging semiconductor devices

Patent metadata

Field	Value
Publication number	US-2015380346-A1
Application number	US-201514849560-A
Country	US
Kind code	A1
Filing date	Sep 9, 2015
Priority date	Jul 1, 2010
Publication date	Dec 31, 2015
Grant date	—

Abstract

A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.

First claim

What is claimed is:

1 . A method of forming a semiconductor package comprising:
providing a conductive base carrier having first and second surfaces; processing the conductive base carrier to have at least a conductive line level with conductive traces separated by spaces; mounting a die on the first surface of the base carrier, the die having die contacts being coupled to the first surface of the base carrier; encapsulating the die with a cap; forming a dielectric layer with openings which exposes portions of the processed conductive base carrier; and forming package contacts which conductively interconnected to the die contacts.

2 . The method of claim 1 wherein processing the conductive base carrier comprises:
patterning the first surface of the conductive base carrier, wherein patterning forms the conductive traces and package on package (PoP) contact posts defined on the first surface of the base carrier, the PoP contact posts extending from the conductive line level to a top surface of the cap, wherein the PoP contact posts facilitate stacking of other device thereon.

3 . The method of claim 2 wherein processing the conductive base carrier comprises patterning the second surface of the base carrier to form first via contacts of a first via level and the dielectric layer exposes portions of the patterned second surface of the base carrier.

4 . The method of claim 2 wherein processing the conductive base carrier comprises:
providing a first mask over the first surface of the base carrier; and
patterning the first mask to form posts on the first surface of the base carrier; and
etching exposed portions of the base carrier not covered by the posts to form the PoP contact posts.

5 . The method of claim 4 wherein processing the conductive base carrier comprises:
providing a second mask over the first surface of the base carrier after forming the PoP contact posts;
patterning the second mask to expose portions of the base carrier; and
etching the exposed portions of the base carrier not covered by the second mask to form the conductive traces, contact pads and die paddle.

6 . The method of claim 5 wherein the die is a wirebond type of die and is mounted onto the die paddle and wirebonds of the die are coupled to the contact pads.

7 . The method of claim 5 wherein the die is a flip chip type of die and the die contacts are coupled to the contact pads.

8 . The method of claim 1 wherein processing the conductive base carrier comprises:
patterning the first surface of the conductive base carrier, wherein patterning forms the conductive traces on the first surface of the base carrier; and
performing a plating process to form PoP contact posts on the first surface of the base carrier extending from the conductive line level to a top surface of the cap, wherein the PoP contact posts facilitate stacking of other device thereon.

9 . The method of claim 1 wherein processing the conductive base carrier comprises patterning the second surface of the base carrier to form the conductive traces and the dielectric layer exposes portions of the patterned second surface of the base carrier.

10 . The method of claim 1 wherein the conductive base carrier comprises a leadframe and the first and second surfaces of the conductive base carrier comprise planar surfaces.

11 . The method of claim 10 wherein processing the conductive base carrier comprises forming trenches in the base carrier through the first surface of the base carrier.

12 . The method of claim 11 wherein the trenches are formed within a die attach region or at periphery of the die attach region of the first surface of the base carrier.

13 . The method of claim 11 wherein the die contacts of the die are disposed in the trenches.

14 . The method of claim 11 comprising dispensing underfill in the space between the die and the base carrier, wherein the underfill also fill the trenches in the base carrier.

15 . The method of claim 11 wherein the die comprises a through-silicon-via (TSV) flip chip having a plurality of TSV contacts coupled to the die contacts.

16 . The method of claim 15 comprising:
removing portion of the cap to expose top surfaces of the TSV contacts; and
mounting at least one device over the die, wherein the at least one device comprises device contacts and are coupled to the exposed top surfaces of the TSV contacts.

17 . The method of claim 15 comprising:
removing portion of the cap to expose top surfaces of the TSV contacts;
forming a first upper dielectric layer over the cap having openings which expose portions of the top surfaces of the TSV contacts;
forming first upper conductive line level having conductive traces coupled to the exposed TSV contacts;
forming a second upper dielectric layer over the first upper conductive line level having openings which expose portions of the conductive traces of the first upper conductive line; and
mounting at least one device on the exposed portions of the conductive traces of the first upper conductive line, the at least one device having device contacts being coupled to the exposed portions of the conductive traces.

18 . The method of claim 17 wherein the at least one device comprises first and second flip chip devices, wherein contacts of the first and second flip chip devices are coupled to exposed portions of the conductive traces.

19 . The method of claim 17 wherein the at least one device comprises a flip chip device and at least one passive component, wherein contacts of the flip chip device and passive component are coupled to exposed portions of the conductive traces.

20 . The method of claim 17 wherein the at least one device comprises a flip chip device and a wirebond type of die stacked over the flip chip device, wherein contacts of the flip chip device and wirebonds of the wirebond type of die are coupled to exposed portions of the conductive traces.

Assignees

• Utac Headquarters Pte Ltd

Inventors

• Wang Chuen Khiang
• Suthiwongsunthorn Nathapong
• Sae Le Kriangsak
• Dimaano Antonio Jr B
• Ng Catherine Bee Liang
• Gan Richard Te
• Eng Kian Teng

Classifications

• H10P14/47

  Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/752

  between stacked chips · CPC title