FinFETs with Different Fin Heights

Patent metadata

Field	Value
Publication number	US-2015111355-A1
Application number	US-201514591838-A
Country	US
Kind code	A1
Filing date	Jan 7, 2015
Priority date	Nov 20, 2009
Publication date	Apr 23, 2015
Grant date	—

Abstract

An integrated circuit structure includes a semiconductor substrate including a first portion in a first device region, and a second portion in a second device region. A first semiconductor fin is over the semiconductor substrate and has a first fin height. A second semiconductor fin is over the semiconductor substrate and has a second fin height. The first fin height is greater than the second fin height.

First claim

What is claimed is:

1 . A method comprising:
forming a first shallow trench isolation (STI) region and a second STI region in a semiconductor substrate, the first STI region being in a first device region, and the second STI region being in a second device region; forming a first mask covering the second device region; recessing the first STI region to a first depth, a portion of the semiconductor substrate extending from the recessed first STI region forming a first semiconductor fin, the first depth being from a top surface of the first semiconductor fin to a top surface of the recessed first STI region; removing the first mask; forming a second mask covering the first device region; and recessing the second STI region to a second depth different from the first depth, a portion of the semiconductor substrate extending from the recessed second STI region forming a second semiconductor fin, the second depth being from a top surface of the second semiconductor fin to a top surface of the recessed second STI region.

2 . The method of claim 1 further comprising:
removing the second mask;
forming a first gate dielectric and a second gate dielectric on top surfaces and sidewalls of the first semiconductor fin and the second semiconductor fin, respectively; and
forming a first gate electrode and a second gate electrode on the first gate dielectric and the second gate dielectric, respectively, the first semiconductor fin, the first gate dielectric, and the first gate electrode forming a first fin field-effect transistor (FinFET), and the second semiconductor fin, the second gate dielectric, and the second gate electrode forming a second FinFET.

3 . The method of claim 2 , wherein the first FinFET and the second FinFET are FinFETs of a same static random access memory cell.

4 . The method of claim 2 , wherein the first FinFET is a p-type FinFET and the second FinFET is an n-type FinFET.

5 . The method of claim 1 , wherein the difference between the first depth and the second depth is greater than about 5 nm.

6 . The method of claim 1 , wherein a ratio of the first depth to the second depth is greater than about 1.25.

7 . The method of claim 1 , wherein the first STI region has a bottom surface level with a bottom surface of the second STI region.

8 . The method of claim 1 , wherein the first depth is greater than the second depth.

9 . The method of claim 1 , wherein a portion of the semiconductor substrate is between the first semiconductor fin and the second semiconductor fin, the top surfaces of the first semiconductor fin, the second semiconductor fin, and the portion of the semiconductor substrate being level with each other.

10 . A method comprising:
forming a first shallow trench isolation (STI) region and a second STI region in a semiconductor substrate, the first STI region being in a first device region, and the second STI region being in a second device region; doping the first STI region with a first impurity to a first impurity concentration; doping the second STI region with a second impurity to a second impurity concentration different from the first impurity concentration; and simultaneously recessing the first STI region and the second STI region, a portion of the semiconductor substrate extending from the recessed first STI region forming a first semiconductor fin, and a portion of the semiconductor substrate extending from the recessed second STI region forming a second semiconductor fin.

11 . The method of claim 10 , wherein the first semiconductor fin has a first fin height from a top surface of the recessed first STI region to a top surface of the first semiconductor fin, and wherein the second semiconductor fin has a second fin height from a top surface of the recessed second STI region to a top surface of the second semiconductor fin, the second fin height being different than the first fin height.

12 . The method of claim 11 , wherein first fin height is greater than the second fin height.

13 . The method of claim 11 , wherein a ratio of the first fin height to the second fin height is greater than about 1.25.

14 . The method of claim 11 , wherein a difference between the first fin height and the second fin height is greater than about 5 nm.

15 . The method of claim 10 further comprising:
forming a first gate dielectric and a second gate dielectric on top surfaces and sidewalls of the first semiconductor fin and the second semiconductor fin, respectively; and
forming a first gate electrode and a second gate electrode on the first gate dielectric and the second gate dielectric, respectively, the first semiconductor fin, the first gate dielectric, and the first gate electrode forming a first fin field-effect transistor (FinFET), and the second semiconductor fin, the second gate dielectric, and the second gate electrode forming a second FinFET.

16 . The method of claim 15 , wherein the first FinFET is a p-type FinFET, and the second FinFET is an n-type FinFET, and wherein the first FinFET and the second FinFET are FinFETs of a same static random access memory cell.

17 . The method of claim 10 , wherein the first device region and the second device region are different types of regions selected from the group consisting essentially of a logic core region, a memory region, an analog region, an input/output (IO) region, and a dummy region.

18 . A method comprising:
forming a first shallow trench isolation (STI) region and a second STI region in a semiconductor substrate, the first STI region being in a first device region, and the second STI region being in a second device region, a first portion of the semiconductor substrate extending from the first STI region forming a first semiconductor fin, and a second portion of the semiconductor substrate extending from the second STI region forming a second semiconductor fin, the first STI region having a first depth from a top surface of the first STI region to a bottom surface of the first STI region, the second STI region having a second depth from a top surface of the second STI region to a bottom surface of the second STI region, the second depth being different than the first depth; forming a first gate dielectric and a second gate dielectric on top surfaces and sidewalls of the first semiconductor fin and the second semiconductor fin, respectively; and forming a first gate electrode and a second gate electrode on the first gate dielectric and the second gate dielectric, respectively, top surfaces of the first gate electrode and the second gate electrode being level with each other, the first semiconductor fin, the first gate dielectric, and the first gate electrode forming a first fin field-effect transistor (FinFET), and the second semiconductor fin, the second gate dielectric, and the second gate electrode forming a second FinFET.

19 . The method of claim 18 , wherein the forming the first STI region and the second STI region comprises:
forming a first mask covering the second device region, wherein the first device region is not covered by the first mask; recessing the first STI region to a first depth, wherein the first portion of the semiconductor substrate adjoining a removed portion of the first STI region forms the first semiconductor fin; removing the first mask; forming a second mask covering the first device region, wherein the second device region is not covered by the second mask; and recessing the second STI region to a second depth different from the first depth, wherein the second portion of the semico

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Lee Tsung-Lin
• Yeh Chih Chieh
• Chang Chang-Yun
• Yuan Feng

Classifications

• H10P30/22

  using masks · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title