Quasi-monolithic integrated packaging architecture with mid-die serializer/deserializer

Patent metadata

Field	Value
Publication number	US-12599033-B2
Application number	US-202117557166-A
Country	US
Kind code	B2
Filing date	Dec 21, 2021
Priority date	Dec 21, 2021
Publication date	Apr 7, 2026
Grant date	Apr 7, 2026

Abstract

A microelectronic assembly is provided, comprising: a first integrated circuit (IC) die having a first connection to a first serializer/deserializer (SERDES) circuit and a second connection to a second SERDES circuit; a second IC die having the first SERDES circuit; and a third IC die having the second SERDES circuit, in which the first IC die is in a first layer, the second IC die and the third IC die are in a second layer not coplanar with the first layer, the first layer and the second layer are coupled by interconnects having a pitch of less than 10 micrometers between adjacent ones of the interconnects, and the first SERDES circuit and the second SERDES circuit are coupled by a conductive pathway.

First claim

The invention claimed is:

1 . A microelectronic assembly, comprising:
a first integrated circuit (IC) die that is a single die; a plurality of interconnects coupled to the first IC die, the plurality of interconnects arranged at a pitch of less than 10 micrometers between adjacent ones of the interconnects; a second IC die coupled to a first portion of the plurality of interconnects, the second IC die having a first SERDES circuit; and a third IC die coupled to a second portion of the plurality of interconnects, the third IC die having a second SERDES circuit, wherein:
the first IC die is in a first layer,
the second IC die and the third IC die are in a second layer,
the second layer is not coplanar with the first layer, and
the first SERDES circuit and the second SERDES circuit are coupled by a conductive pathway.

2 . The microelectronic assembly of claim 1 , wherein:
the conductive pathway is through an interposer, and the second layer is between the first layer and the interposer.

3 . The microelectronic assembly of claim 2 , wherein the interposer comprises an organic package substrate.

4 . The microelectronic assembly of claim 2 , wherein the interposer comprises a fourth IC die.

5 . The microelectronic assembly of claim 1 , wherein the conductive pathway is through a redistribution layer between the first layer and the second layer.

6 . The microelectronic assembly of claim 1 , wherein:
a first connection between the first IC die and the first SERDES circuit comprises at least one of the interconnects, and a second connection between the first IC die and the second SERDES circuit comprises at least another of the interconnects.

7 . The microelectronic assembly of claim 1 , further comprising:
a fourth IC die in the first layer, the fourth IC die having a third connection to a third SERDES circuit; and a fifth IC die in the second layer, the fifth IC die having the third SERDES circuit, wherein:
the third connection comprises at least one of the interconnects,
the conductive pathway is a first conductive pathway, and
the first SERDES circuit and the third SERDES circuit are coupled by a second conductive pathway.

8 . The microelectronic assembly of claim 1 , wherein the second IC die and the third IC die are part of a fourth IC die.

9 . An IC package, comprising:
a first IC die in a first layer, wherein the first IC die is a single die; a second IC die and a third IC die in a second layer; and an interposer, wherein:
the second layer is between the first layer and the interposer,
the first layer is coupled to the second layer by interconnects having a pitch of less than 10 micrometers between adjacent ones of the interconnects,
a first circuit block in the first IC die is coupled to and at least partially vertically overlapping a first SERDES circuit in the second IC die,
a second circuit block in the first IC die is coupled to and at least partially vertically overlapping a second SERDES circuit in the third IC die, and
the first SERDES circuit and the second SERDES circuit are coupled by a conductive pathway through the interposer.

10 . The IC package of claim 9 , further comprising:
a fourth IC die in the first layer coupled to a third SERDES circuit; and a fifth IC die having the third SERDES circuit, wherein:
the fifth IC die is in the second layer,
the conductive pathway is a first conductive pathway, and
the first SERDES circuit and the third SERDES circuit are coupled by a second conductive pathway through the interposer.

11 . The IC package of claim 10 , wherein the second SERDES circuit and the third SERDES circuit are coupled by a third conductive pathway through the interposer.

12 . The IC package of claim 9 , wherein the interposer comprises a package substrate with layers of organic dielectric material with conductive traces between the layers of organic dielectric material and conductive vias coupling the conductive traces through the layers of organic dielectric material.

13 . The IC package of claim 9 , wherein the interposer comprises a fourth IC die.

14 . The IC package of claim 13 , wherein the second layer is coupled to the interposer with interconnects having a pitch of less than 10 micrometers between adjacent ones of the interconnects.

15 . The IC package of claim 9 , wherein the conductive pathway comprises a conductive trace through the interposer without any intervening circuits.

16 . The IC package of claim 9 , wherein the second layer comprises a dielectric material with through-dielectric vias (TDVs) in the dielectric material surrounding the second IC die and the third IC die.

17 . An IC structure, comprising:
a first circuit in a single die in a first layer, the first circuit coupled to a first SERDES circuit in a second layer by a first set of interconnects having a pitch of less than 10 micrometers between adjacent ones of the first set of interconnects; a second circuit in the single die in the first layer, the second circuit coupled to a second SERDES circuit in the second layer by second first set of interconnects having a pitch of less than 10 micrometers between adjacent ones of the second set of interconnects; and a conductive pathway between the first SERDES circuit and the second SERDES circuit, wherein:
the first layer is not coplanar with the second layer.

18 . The IC structure of claim 17 , wherein the first circuit and the second circuit are in a first IC die, the first SERDES circuit is in a second IC die, and the second SERDES circuit is in a third IC die.

19 . The IC structure of claim 17 , wherein:
a first transmission (TX) block of the first SERDES circuit is coupled by a first conductive trace to a first receiver (RX) block of the second SERDES circuit, a second RX block of the first SERDES circuit is coupled by a second conductive trace to a second TX block of the second SERDES circuit, and the conductive pathway comprises the first conductive trace and the second conductive trace.

20 . The IC structure of claim 17 , wherein the first circuit is at least partially vertically overlapping the first SERDES circuit, and the second circuit is at least partially vertically overlapping the second SERDES circuit.

Assignees

• Intel Corp

Inventors

• Pasdast Gerald S
• Elsherbini Adel A
• Nassif Nevine
• Molnar Carleton L
• Rajan Vivek Kumar
• Wang Peipei
• Liff Shawna M
• Singh Tejpal
• Swan Johanna M

Classifications

• H10W70/635

  Through-vias · CPC title

• H10W70/69

  Insulating materials thereof · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W72/823

  Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip · CPC title