Bilayer memory stacking with lines shared between bottom and top memory layers

Patent metadata

Field	Value
Publication number	US-12599032-B2
Application number	US-202117409877-A
Country	US
Kind code	B2
Filing date	Aug 24, 2021
Priority date	Aug 24, 2021
Publication date	Apr 7, 2026
Grant date	Apr 7, 2026

Abstract

IC devices implementing bilayer stacking with lines shared between bottom and top memory layers, and associated systems and methods, are disclosed. An example IC device includes a support structure, a front end of line (FEOL) layer and a back end of line (BEOL) layer. The BEOL layer includes a first memory cell in a first layer over the support structure, an electrically conductive line in a second layer, above the first layer, and a second memory cell in a third layer, above the second layer. The line could be one of a wordline, a bitline, or a plateline that is shared between the first and second memory cells. In particular, bilayer stacking line sharing is such that only one line is provided as a line to be shared between one or more of the memory cells of the first layer and one or more memory cells of the third layer.

First claim

The invention claimed is:

1 . An integrated circuit (IC) device, comprising:
a substrate; a first memory cell in a first layer over the substrate; a line comprising an electrically conductive material, in a second layer over the substrate, where the first layer is between the second layer and the substrate; and a second memory cell in a third layer over the substrate, where the second layer is between the first layer and the third layer, wherein:
the line includes a first face and a second face, the second face being opposite the first face and being further away from the substrate than the first face,
the first memory cell is coupled to the first face of the line and includes a first capacitor,
the second memory cell is coupled to the second face of the line and includes a second capacitor,
a channel material of a transistor of the first memory cell is closer to the first face of the line than to the second face of the line and is between the line and contacts of a source region and a drain region of the transistor of the first memory cell,
each of the first capacitor and the second capacitor includes an electrode having a U-shape, and
the U-shape of the first capacitor is oriented in the IC device upside down compared to the U-shape of the second capacitor.

2 . The IC device according to claim 1 , wherein the line is a wordline for the first memory cell and the second memory cell.

3 . The IC device according to claim 1 , wherein:
each of the first memory cell and the second memory cell includes a thin-film transistor (TFT), the first capacitor is coupled to the TFT of the first memory cell, and the second capacitor is coupled to the TFT of the second memory cell.

4 . The IC device according to claim 1 , wherein:
the contacts of the source region and the drain region of the transistor of the first memory cell are between the channel material of the transistor of the first memory cell and the substrate.

5 . The IC device according to claim 4 , wherein the line is a wordline for the first memory cell and the second memory cell.

6 . The IC device according to claim 4 , wherein:
a channel material of a transistor of the second memory cell is closer to the second face of the line than to the first face of the line and is between the line and contacts of a source region and a drain region of the transistor of the second memory cell.

7 . The IC device according to claim 6 , wherein the line is a wordline for the first memory cell and the second memory cell.

8 . The IC device according to claim 6 , wherein:
the channel material of the transistor of the second memory cell is between the contacts of the source region and the drain region of the transistor of the second memory cell and the second face of the line.

9 . The IC device according to claim 8 , wherein the line is a wordline for the first memory cell and the second memory cell.

10 . An integrated circuit (IC) package, comprising:
an IC device; and a further IC component, coupled to the IC device, wherein the IC device includes:
a die,
a first memory cell in a first layer over the die,
a first line comprising an electrically conductive material, in a second layer over the die, where the first layer is between the second layer and the die,
a second memory cell in a third layer over the die, where the second layer is between the first layer and the third layer,
a second line comprising an electrically conductive material, in a fourth layer over the die, where the third layer is between the second layer and the fourth layer, and
a third memory cell in a fifth layer over the die, where the fourth layer is between the third layer and the fifth layer,
wherein:
each of the first memory cell and the second memory cell is coupled to the first line,
each of the second memory cell and the third memory cell is coupled to the second line,
the first memory cell includes a first capacitor,
the second memory cell includes a second capacitor,
each of the first capacitor and the second capacitor includes an electrode having a U-shape, and
the U-shape of the first capacitor is oriented in the IC device upside down compared to the U-shape of the second capacitor.

11 . The IC package according to claim 10 , wherein:
the first line is a wordline or a plateline for each of the first memory cell and the second memory cell, and the second line is a bitline for each of the second memory cell and the third memory cell.

12 . The IC package according to claim 10 , wherein:
the first line is a wordline for each of the first memory cell and the second memory cell, and the second line is a bitline or a plateline for each of the second memory cell and the third memory cell.

13 . The IC package according to claim 10 , wherein:
the first line is a bitline or a plateline for each of the first memory cell and the second memory cell, and the second line is a wordline for each of the second memory cell and the third memory cell.

14 . The IC package according to claim 10 , wherein:
the first line is a bitline for each of the first memory cell and the second memory cell, and the second line is a wordline or a plateline for each of the second memory cell and the third memory cell.

15 . An integrated circuit (IC) device, comprising:
a first memory cell comprising a capacitor in a first layer and a transistor in a second layer; a second memory cell comprising a transistor in a third layer and a capacitor in a fourth layer; a first via at least partially in at least one of the first layer and the second layer; and a second via at least partially in at least one of the third layer and the fourth layer, wherein:
the second layer is between the first layer and the third layer,
the third layer is between the second layer and the fourth layer,
the first via tapers in a direction from the third layer to the first layer, and
the second via tapers in a direction from the first layer to the third layer.

16 . The IC device according to claim 15 , wherein:
each of the capacitor of the first memory cell and the capacitor of the second memory cell includes an electrode having a U-shape, and the U-shape of the capacitor of the first memory cell is upside down with respect to the U-shape of the capacitor of the second memory cell.

17 . The IC device according to claim 16 , further comprising a conductive line in a layer between the second layer and the third layer, wherein:
the line includes a first face and a second face, the second face being opposite the first face and being further away from the first layer than the first face, the first memory cell is coupled to the first face of the line, and the second memory cell is coupled to the second face of the line.

18 . The IC device according to claim 17 , wherein the line is a wordline for the first memory cell and the second memory cell.

19 . The IC device according to claim 17 , wherein the line is conductively coupled to a gate of the transistor of the first memory cell and a gate of the transistor of the second memory cell.

20 . The IC device according to claim 15 , wherein the transistor of the first memory cell is closer to the transistor of the second memory cell than the capacitor of the first memory cell.

Assignees

• Intel Corp

Inventors

• Sharma Abhishek A
• Sato Noriyuki
• Le Van H
• Atanasov Sarah
• Yoo Hui Jae
• Sell Bernhard
• Wang Pei-Hua
• Lajoie Travis W
• Ku Chieh-Jen
• Alzate-Vinasco Juan G
• Hamzaoglu Fatih

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10W90/792

  between multiple chips · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title