Semiconductor device

Patent metadata

Field	Value
Publication number	US-12598987-B2
Application number	US-202418590793-A
Country	US
Kind code	B2
Filing date	Feb 28, 2024
Priority date	Aug 27, 2020
Publication date	Apr 7, 2026
Grant date	Apr 7, 2026

Abstract

A semiconductor device including a transistor on a substrate; an interlayer insulating layer on the transistor; a first metal-containing layer on the interlayer insulating layer; and a second metal-containing layer on the first metal-containing layer, wherein the second metal-containing layer includes a resistor, the resistor includes a first insulating layer on the first metal-containing layer; a resistor metal layer on the first insulating layer, and a second insulating layer on the resistor metal layer, and the resistor metal layer includes a recessed side surface.

First claim

What is claimed is:

1 . A method of manufacturing a semiconductor device, the method comprising:
forming a transistor on a substrate; forming a first metal-containing layer on the transistor; forming sequentially a first insulating layer, a resistor metal layer and a second insulating layer on the first metal-containing layer; forming a first hard mask pattern on the second insulating layer; performing a first etching process of the second insulating layer using the first hard mask pattern as an etch mask for the first etching process, wherein the resistor metal layer is an etch stop layer for the first etching process; and performing a second etching process of the resistor metal layer using the first hard mask pattern as an etch mask for the second etching process, wherein the second etching process includes forming a curved concave recessed side surface of the resistor metal layer.

2 . The method of claim 1 , wherein a ratio of a thickness of the first insulating layer to a thickness of the second insulating layer ranges from 0.8 to 1.2.

3 . The method of claim 1 , wherein the second etching process includes etching the resistor metal layer to expose a top surface of the first insulating layer.

4 . The method of claim 1 , wherein the first etching process includes etching the second insulating layer and the resistor metal layer, and wherein at least a portion of the resistor metal layer remains on an entire top surface of the first metal-containing layer.

5 . The method of claim 1 , wherein a center portion of the side surface of the resistor metal layer extends along a curve and further inwardly in the resistor metal layer than a top portion of the side surface of the resistor metal layer and extends along a curve and further inwardly in the resistor metal layer than a bottom portion of the side surface of the resistor metal layer.

6 . The method of claim 1 , further comprising forming an etch stop layer on an entire top surface of the first metal-containing layer, and
wherein the etch stop layer includes a protruding portion protruding toward the recessed side surface of the resistor metal layer.

7 . The method of claim 6 , further comprising:
forming an interlayer insulating layer on the etch stop layer; and forming a first opening and a second opening by etching the interlayer insulating layer, and wherein a top surface of the resistor metal layer is exposed by the first opening.

8 . The method of claim 7 , wherein the first metal-containing layer includes a lower interconnection line, and
wherein a top surface of the lower interconnection line is exposed by the second opening.

9 . The method of claim 7 , further comprising forming a upper interconnection line on the interlayer insulating layer,
wherein a bottom surface of the upper interconnection line has a stepped profile.

10 . The method of claim 1 , wherein a lowermost level of a bottom surface of the resistor metal layer is located at a same level as a lowermost level of a top surface of the first insulating layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lim Seonghun
• You Wookyung
• Lee Kyoungwoo
• Jung Juyoung
• Kim Il Sup
• Kim Chin
• Park Kyoungpil
• Park Jinhyung

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10D84/817

  Combinations of field-effect devices and resistors only · CPC title

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title