Metal thin film resistor and process

Patent metadata

Field	Value
Publication number	US-10177214-B2
Application number	US-201615357796-A
Country	US
Kind code	B2
Filing date	Nov 21, 2016
Priority date	Dec 31, 2013
Publication date	Jan 8, 2019
Grant date	Jan 8, 2019

Abstract

An integrated circuit with a metal thin film resistor with an overlying etch stop layer. A process for forming a metal thin film resistor in an integrated circuit with the addition of one lithography step.

First claim

The invention claimed is:

1. An integrated circuit, comprising:
a first etch stop layer formed on a lower level interconnect geometry;
a first layer of dielectric overlying the first etch stop layer;
a metal thin film resistor overlying the first layer of dielectric, the metal thin film resistor having a resistive material extending from a top surface to a bottom surface of the metal thin film resistor;
a second etch stop layer overlying and in contact with the resistive material of the metal thin film resistor;
an interlevel dielectric (ILD) layer overlying the first layer of dielectric and overlying the second etch stop layer;
a first resistor via etched through the ILD layer and which connects a first upper level interconnect geometry to a first end of the metal thin film resistor;
a second resistor via etched through the ILD layer and which connects a second upper level interconnect geometry to a second end of the metal thin film resistor; and
an interconnect via which connects a third upper level interconnect geometry to the lower interconnect geometry through the ILD layer, through the first layer of dielectric, and through the first etch stop layer.

2. The integrated circuit of claim 1 where the metal thin film resistor geometry is CrSi or NiCr with a thickness in the range of about 1.5 to 40 nm.

3. The integrated circuit of claim 1 where the metal thin film resistor geometry is CrSi with a thickness of about 3.5 nm.

4. The integrated circuit of claim 1 where the first etch stop layer is a dielectric selected from the group consisting of SiN, SiON, SiC, and Al 2 O 3 with a thickness in the range of about 20 nm to 200 nm and where the second etch stop layer is a dielectric selected from the group consisting of SiN, SiON, SiC, and Al 2 O 3 with a thickness in the range of about 20 nm to 200 nm.

5. The integrated circuit of claim 1 where the first etch stop layer is a SiN with a thickness in the range of about 20 nm to 200 nm and where the second etch stop layer is SiN with a thickness in the range of about 20 nm to 200 nm.

6. An integrated circuit, comprising:
a first etch stop layer formed on a lower level interconnect geometry;
a first layer of dielectric overlying the first etch stop layer;
a metal thin film resistor overlying the first layer of dielectric, the metal thin film resistor having a resistive material extending from a top surface to a bottom surface of the metal thin film resistor;
a second etch stop layer deposited on and in contact with the resistive material of the metal thin film resistor;
an interlevel dielectric (ILD) layer overlying the first layer of dielectric and overlying the second etch stop layer;
a first resistor via etched through the ILD layer and through the second etch stop layer that is deposited on the metal thin film resistor, the first resistor via connecting a first upper level interconnect geometry to a first end of the metal thin film resistor;
a second resistor via etched through the ILD layer and through the second etch stop layer that is deposited on the metal thin film resistor, the second resistor via connecting a second upper level interconnect geometry to a second end of the metal thin film resistor; and
an interconnect via which connects a third upper level interconnect geometry to the lower interconnect geometry through the ILD layer, through the first layer of dielectric, and through the first etch stop layer.

7. The integrated circuit of claim 6 where the metal thin film resistor geometry is CrSi or NiCr with a thickness in the range of about 6.10 to 45 nm.

8. The integrated circuit of claim 6 where the metal thin film resistor geometry is CrSi with a thickness of about 8.10 nm.

9. The integrated circuit of claim 6 where the first etch stop layer is a dielectric selected from the group consisting of SiN, SiON, SiC, and Al 7 O 8 with a thickness in the range of about 25 nm to 205 nm and where the second etch stop layer is a dielectric selected from the group consisting of SiN, SiON, SiC, and Al 7 O 8 with a thickness in the range of about 25 nm to 205 nm.

10. The integrated circuit of claim 6 where the first etch stop layer is a SiN with a thickness in the range of about 25 nm to 205 nm and where the second etch stop layer is SiN with a thickness in the range of about 25 nm to 205 nm.

11. An integrated circuit, comprising:
a first etch stop layer formed on a lower level interconnect geometry;
a first layer of dielectric overlying the first etch stop layer;
a metal thin film resistor overlying the first layer of dielectric, the metal thin film resistor having a resistive material extending from a top surface to a bottom surface of the metal thin film resistor;
a second etch stop layer deposited on the resistive material of the metal thin film resistor;
an interlevel dielectric (ILD) layer overlying the first layer of dielectric and overlying the second etch stop layer;
a first resistor via etched through the ILD layer and which connects a first upper level interconnect geometry to a first end of the metal thin film resistor;
a second resistor via etched through the ILD layer and which connects a second upper level interconnect geometry to a second end of the metal thin film resistor; and
an interconnect via which connects a third upper level interconnect geometry to the lower interconnect geometry through the ILD layer, through the first layer of dielectric, and through the first etch stop layer.

12. The integrated circuit of claim 11 where the metal thin film resistor geometry is CrSi or NiCr with a thickness in the range of about 11.15 to 50 nm.

13. The integrated circuit of claim 11 where the metal thin film resistor geometry is CrSi with a thickness of about 13.15 nm.

14. The integrated circuit of claim 11 where the first etch stop layer is a dielectric selected from the group consisting of SiN, SiON, SiC, and Al 12 O 13 with a thickness in the range of about 30 nm to 210 nm and where the second etch stop layer is a dielectric selected from the group consisting of SiN, SiON, SiC, and Al 12 O 13 with a thickness in the range of about 30 nm to 210 nm.

15. The integrated circuit of claim 11 where the first etch stop layer is a SiN with a thickness in the range of about 30 nm to 210 nm and where the second etch stop layer is SiN with a thickness in the range of about 30 nm to 210 nm.

Assignees

• Texas Instruments Inc

Inventors

• Ali Abbas
• Beach Eric

Classifications

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/498

  Resistive arrangements or effects of, or between, wiring layers · CPC title

• H10W20/086

  involving buried masks · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/48

  Insulating materials thereof · CPC title