High-voltage semiconductor device

Patent metadata

Field	Value
Publication number	US-2022013520-A1
Application number	US-202016925622-A
Country	US
Kind code	A1
Filing date	Jul 10, 2020
Priority date	Jul 10, 2020
Publication date	Jan 13, 2022
Grant date	—

Abstract

A high-voltage semiconductor device includes a substrate, a body region, a well region, a bulk region, a source, a drain, an isolation region, a gate structure, and a resistor. The body region and the well region are disposed in the substrate. The bulk region and the source are disposed in the body region. The drain is disposed in the well region. The isolation region is disposed on the well region. The isolation region is disposed between the drain and the source. The gate structure is disposed on the substrate. The gate structure extends onto a portion of the isolation region. The resistor is disposed on the isolation region. The resistor is electrically connected to the bulk region and the drain, or the resistor is electrically connected to the drain and/or the source.

First claim

What is claimed is:

1 . A high-voltage semiconductor device, comprising:
a substrate; a body region and a well region disposed in the substrate and spaced apart from each other, wherein the body region has a first conductivity type and the well region has a second conductivity type opposite to the first conductivity type; a bulk region and a source disposed in the body region and spaced apart from each other, wherein the bulk region has the first conductivity type and the source has the second conductivity type; a drain disposed in the well region; an isolation region disposed on the well region and between the drain and the source; a gate structure disposed on the substrate and extending onto a portion of the isolation region; and a resistor disposed on the isolation region and electrically connected to the bulk region and the drain or electrically connected to the drain and/or the source.

2 . The device as claimed in claim 1 , wherein the drain has a profile surrounded by the resistor.

3 . The device as claimed in claim 2 , wherein the gate structure has an inner profile, and the resistor is between the inner profile and the profile of the drain.

4 . The device as claimed in claim 1 , wherein the drain has a ring shape and the resistor has a spiral shape or a plurality of concentric ring shapes.

5 . The device as claimed in claim 4 , wherein the plurality of concentric ring shapes comprise a circle, an ellipse, or a combination thereof.

6 . The device as claimed in claim 1 , wherein the drain has a finger shape and the resistor has a spiral finger shape or a plurality of concentric finger shapes.

7 . The device as claimed in claim 1 , further comprising:
at least one conductor disposed on the resistor; an insulation layer disposed between the at least one conductor and the resistor; and a plurality of contacts disposed in the insulation layer, wherein the resistor is connected in parallel with the at least one conductor through the contacts.

8 . The device as claimed in claim 7 , wherein the at least one conductor extends in a lengthwise direction of the resistor, and the at least one conductor partially overlaps at least a portion of a vertically projected region of the resistor.

9 . The device as claimed in claim 7 , wherein a vertically projected region of the at least one conductor is smaller than a vertically projected region of the resistor.

10 . The device as claimed in claim 7 , wherein a material of the at least one conductor comprises amorphous silicon, polycrystalline silicon, metal nitride, metal silicide, conductive metal oxide, metal, an alloy thereof, or a combination thereof.

11 . The device as claimed in claim 1 , wherein a material of the resistor comprises amorphous silicon, polycrystalline silicon, metal nitride, metal silicide, conductive metal oxide, metal, an alloy thereof, or a combination thereof.

12 . The device as claimed in claim 1 , further comprising:
a first doped region disposed under the isolation region; a second doped region disposed under the first doped region and forming a junction with the first doped region, wherein the second doped region and the first doped region have opposite conductivity types.

13 . The device as claimed in claim 12 , wherein at least one of the first doped region and the second doped region comprises at least two sub-implant regions with different implant concentrations.

14 . The device as claimed in claim 13 , wherein one of the sub-implant regions with a higher implant concentration is adjacent to the junction, and another one of the sub-implant regions with a lower implant concentration is distant from the junction.

15 . The device as claimed in claim 1 , wherein the drain comprises two doped regions with opposite conductivity types.

16 . The device as claimed in claim 15 , wherein the resistor is connected to the two doped regions respectively.

17 . The device as claimed in claim 15 , wherein the two doped regions are spaced apart from each other.

18 . The device as claimed in claim 15 , further comprising another doped region disposed between the isolation region and the two doped regions.

19 . The device as claimed in claim 1 , wherein the bulk region is connected to ground.

20 . The device as claimed in claim 1 , wherein the resistor has a plurality of resistance segments connected in series, and the segments have shapes of an arc, a straight line, or a combination thereof.

Assignees

• Vanguard Int Semiconduct Corp

Inventors

• Ho Yu-Hao
• Chiang Hsiao-Ling
• Chiang Yueh-Chu
• Huang Yi-Hsiang

Classifications

• H10D30/603

  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS] · CPC title

• H10D84/151

  LDMOS having built-in components · CPC title

• H10D12/411

  Insulated-gate bipolar transistors [IGBT] · CPC title

• H10D64/516

  the thicknesses being non-uniform · CPC title

• H10D64/115

  Resistive field plates, e.g. semi-insulating field plates · CPC title