Epitaxial formation with treatment and semiconductor devices resulting therefrom

Patent metadata

Field	Value
Publication number	US-12598937-B2
Application number	US-202318171508-A
Country	US
Kind code	B2
Filing date	Feb 20, 2023
Priority date	Feb 20, 2023
Publication date	Apr 7, 2026
Grant date	Apr 7, 2026

Abstract

In an embodiment, a method includes forming a first semiconductor fin and a second semiconductor fin over a front-side of a substrate; etching a first recess in the first semiconductor fin and a second recess in the second semiconductor fin; forming a first epitaxial region in the first recess and first epitaxial nodules along sidewalls of the first recess; forming a second epitaxial region in the second recess and second epitaxial nodules along sidewalls of the second recess; flowing first precursors to remove the first epitaxial nodules; depositing an interlayer dielectric over the first epitaxial region and the second epitaxial region; etching a first opening in the interlayer dielectric to expose the first epitaxial region; forming a first epitaxial cap on the first epitaxial region and third epitaxial nodules over the interlayer dielectric; and flowing second precursors to remove the third epitaxial nodules.

First claim

What is claimed is:

1 . A method comprising:
forming a first semiconductor fin and a second semiconductor fin over a front-side of a substrate; etching a first recess in the first semiconductor fin; forming a first epitaxial region in the first recess and first epitaxial nodules over the first semiconductor fin; flowing first precursors to remove the first epitaxial nodules; depositing an interlayer dielectric over the first epitaxial region; etching a first opening in the interlayer dielectric to expose the first epitaxial region; forming a first epitaxial cap on the first epitaxial region and third epitaxial nodules over the interlayer dielectric; and flowing second precursors to remove the third epitaxial nodules.

2 . The method of claim 1 , wherein the first epitaxial region comprises a first material in crystalline form, and wherein each of the first epitaxial nodules comprises the first material in a non-crystalline form.

3 . The method of claim 1 , wherein the first precursors comprise fluorine gas and ammonia.

4 . The method of claim 3 , wherein the first precursors are free of chlorine.

5 . The method of claim 3 , wherein the first epitaxial region comprises crystalline silicon.

6 . The method of claim 1 , further comprising, after depositing the interlayer dielectric:
thinning a back-side of the substrate; etching a second opening through the back-side of the substrate to expose a second epitaxial region in the second semiconductor fin; forming a second epitaxial cap on the second epitaxial region and fourth epitaxial nodules over the back-side of the substrate; and flowing third precursors to remove the fourth epitaxial nodules.

7 . The method of claim 6 , wherein the second epitaxial region comprises silicon germanium, and wherein the second epitaxial cap comprises silicon germanium.

8 . The method of claim 6 , wherein the third precursors comprise fluorine gas and hydrogen fluoride.

9 . A method comprising:
forming a source/drain region in a fin; forming a gate structure over the fin; depositing a dielectric layer over the source/drain region and the gate structure; etching an opening in the dielectric layer to expose the source/drain region; forming a dielectric liner over the dielectric layer and over the source/drain region in the opening; etching a portion of the dielectric liner to expose the source/drain region; forming an epitaxial cap over the source/drain region, the epitaxial cap comprising a crystalline form of a first epitaxial material; flowing first precursors over the epitaxial cap, the first precursors having a higher etch selectivity to an amorphous form of the first epitaxial material than to the crystalline form of the first epitaxial material; converting at least a portion of the epitaxial cap into a silicide region; and forming a contact plug over the silicide region within the opening.

10 . The method of claim 9 , wherein forming the epitaxial cap comprises forming first epitaxial nodules along a remaining portion of the dielectric liner within the opening, and wherein the first epitaxial nodules comprise the first epitaxial material in at least one of an amorphous form or a polycrystalline form.

11 . The method of claim 9 , wherein the epitaxial cap comprises silicon, and wherein the first precursors comprise fluorine gas and ammonia gas.

12 . The method of claim 9 , wherein the epitaxial cap comprises silicon germanium, and wherein the first precursors comprise fluorine gas and hydrogen fluoride gas.

13 . The method of claim 9 , wherein the dielectric liner has a first roughness before forming the epitaxial cap, wherein the dielectric liner has a second roughness after flowing the first precursors, and wherein the second roughness is greater than the first roughness.

14 . The method of claim 13 , wherein the second roughness is two to five times the first roughness.

15 . The method of claim 9 , wherein forming the source/drain region comprises:
forming a crystalline form of a second epitaxial material; and depositing second epitaxial nodules along a gate spacer, the second epitaxial nodules comprising a non-crystalline form of the second epitaxial material.

16 . The method of claim 15 , further comprising flowing second precursors over the source/drain region, the second precursors having a higher etch selectivity to the second epitaxial nodules than to the source/drain region.

17 . A method comprising:
forming a dummy gate structure over a fin; forming a gate spacer over the fin and along the dummy gate structure; etching a recess in the fin adjacent to the gate spacer; forming an epitaxial region in the recess and epitaxial nodules along a sidewall of the gate spacer, the sidewall comprising first portions covered by the epitaxial nodules and second portions exposed between the epitaxial nodules; and performing an etch process to remove the epitaxial nodules, performing the etch process comprising etching the second portions of the sidewall of the gate spacer.

18 . The method of claim 17 , wherein performing the etch process comprises increasing a roughness of the sidewall.

19 . The method of claim 17 , wherein the epitaxial region comprises a crystalline material, and wherein the epitaxial nodules comprise a non-crystalline material.

20 . The method of claim 17 , wherein the etch process utilizes etchants comprising at least one of fluorine gas or ammonia.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lo Yi-Chen
• Shih Ding-Kang
• Hung Tsungyu
• Pai Chia-Ling
• Tsai Pang-Yen
• Lin Li-Te
• Lin Pinyen

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/052

  by treatments not introducing additional elements therein · CPC title

• H10W20/033

  in openings in dielectrics · CPC title

• H10D84/0186

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title