Semiconductor structure, method for forming same and layout structure

Patent metadata

Field	Value
Publication number	US-12598733-B2
Application number	US-202217936832-A
Country	US
Kind code	B2
Filing date	Sep 29, 2022
Priority date	Jun 24, 2022
Publication date	Apr 7, 2026
Grant date	Apr 7, 2026

Abstract

A method for forming a semiconductor structure includes the following: a substrate is provided, the substrate including a first area and a second area arranged in sequence in a second direction and T-shaped active pillars located in the first area and the second area and arranged in an array in a first direction and a third direction, the first, second and third directions being perpendicular to one another, and the first and second directions being parallel to a surface of the substrate; T-shaped gate structures located on surfaces of the T-shaped active pillars and bit line structures extending in the third direction are formed in the first area, a plurality of T-shaped gate structures located in the first direction being interconnected; and capacitor structures extending in the second direction is formed in the second area, the bit line structures and the capacitor structures being connected to the T-shaped gate structures.

First claim

What is claimed is:

1 . A method for forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first area and a second area arranged in sequence in a second direction, and T-shaped active pillars located in the first area and the second area and arranged in an array in a first direction and a third direction, the first direction, the second direction and the third direction are perpendicular to one another, and the first direction and the second direction are parallel to a surface of the substrate, wherein each of the T-shaped active pillars comprises a first active pillar and a second active pillar located in the first area and extending in the second direction, and a third active pillar and a fourth active pillar located in the second area and extending in the first direction, and a fifth active pillar located in the second area, and the first active pillar is connected to the third active pillar, and a projection of the first active pillar and the second active pillar jointly on the surface of the semiconductor substrate is a T shape; forming T-shaped gate structures located on surfaces of the T-shaped active pillars and bit line structures extending in the third direction on part of the fourth active pillars in the first area, wherein a plurality of the T-shaped gate structures located in the first direction are interconnected; and forming capacitor structures extending in the second direction on the fifth active pillars in the second area, wherein the bit line structures and the capacitor structures are connected to the T-shaped gate structures.

2 . The method of claim 1 , wherein
wherein forming the T-shaped gate structures located on the surfaces of the T-shaped active pillars and the bit line structures on part of the fourth active pillars in the first area comprises: forming each of the T-shaped gate structures on the surfaces of the first active pillar and the third active pillar; and forming each of the bit line structures extending in the third direction at one end, which is far away from the third active pillar, of the fourth active pillar.

3 . The method of claim 2 , wherein
the T-shaped active pillars are formed by: providing a semiconductor substrate; forming a stacked structure located in the first area and the second area on the surface of the semiconductor structure, the stacked structure comprising first semiconductor layers and second semiconductor layers stacked alternately in the third direction; removing the first semiconductor layers in the first area to expose the second semiconductor layers in the first area; performing thinning processing on the exposed second semiconductor layers to form initial active layers; and processing the initial active layers to form the T-shaped active pillars.

4 . The method of claim 3 , wherein
processing the initial active layers to form the T-shaped active pillars comprises: forming a first sacrificial layer and a first supporting layer on a surface of each of the initial active layers in sequence, wherein the first supporting layer fills between two adjacent ones of the first sacrificial layers; removing part of the first supporting layer, part of the first sacrificial layer and part of the initial active layer in the first area, and part of the stacked structure in the second area, so as to form a plurality of concave grooves arranged at intervals in the first direction; and removing part of the initial active layer in the second direction to form a first space, wherein the remaining initial active layer forms the T-shaped active pillar.

5 . The method of claim 4 , further comprising:
filling an isolating material in the concave grooves to form an isolating layer after forming the concave grooves.

6 . The method of claim 5 , wherein
the first active pillar, the second active pillar, the third active pillar and the fourth active pillar are formed by: removing part of the first sacrificial layer in the first direction and the second direction to expose part of the initial active layer and form a second space, wherein parts, extending in the first direction and in the second direction, of the exposed part of the initial active layer respectively form the first active pillar and the third active pillar; parts, extending in the first direction and in the second direction, of the un-exposed part of the initial active layer respectively form the second active pillar and the fourth active pillar; and the second space contains the first space.

7 . The method of claim 6 , wherein
forming each of the T-shaped gate structures on the surfaces of the first active pillar and the third active pillar comprises: forming a gate dielectric layer and a gate conductive layer on the surfaces of the first active pillar and the third active pillar in sequence to form the T-shaped gate structure, wherein the gate conductive layer fills the second space.

8 . The method of claim 6 , wherein
forming each of the bit line structures extending in the third direction at one end, which is far away from the third active pillar, of the fourth active pillar comprises: removing part of the first sacrificial layer and part of the isolating layer on the sidewall of the fourth active pillar to form a bit line groove, wherein the bit line groove exposes one end, which is far away from the third active pillar, of the fourth active pillar, and part of the isolating layer remains between two adjacent ones of the T-shaped active pillars in the first direction; and filling a bit line metal material in the bit line groove to form the bit line structure.

9 . The method of claim 4 , wherein
the fifth active pillars extends in the second direction; the fifth active pillars are formed by: removing the first semiconductor layers in the remaining stacked structures in the second area and the isolating layer located in the second area to expose the second semiconductor layers; and performing thinning processing on the exposed second semiconductor layers to form the fifth active pillars, wherein each of the fifth active pillars is connected to corresponding one of the second active pillars.

10 . The method of claim 9 , wherein
each of the fifth active pillars comprises a first sub-pillar, a second sub-pillar and a third sub-pillar arranged in the second direction in sequence; and wherein forming the capacitor structures in the second area comprises: forming a second supporting layer on a surface of each first sub-pillar, wherein the second supporting layer fills between two adjacent ones of the first sub-pillars, and the first supporting layer and the second supporting layer constitute a supporting structure of the semiconductor structure; forming a second sacrificial layer on a surface of each second sub-pillar, wherein the second sacrificial layer fills between two adjacent ones of the second sub-pillars; forming a third semiconductor layer on a surface of each third sub-pillar; forming a first electrode layer on a surface of the third semiconductor layer and a sidewall of the second sacrificial layer; forming a protective layer on surface of the first electrode layer and in a gap formed between surfaces of the first electrode layer; removing the second sacrificial layer and the first electrode layer located on the sidewall of the second sub-pillar to expose the second sub-pillar and the sidewall of the second supporting layer; removing the protective layer to expose the remaining first electrode layer; forming a dielectric layer on the surfaces of the second sub-pillar and the first electrode layer; and forming a second electrode layer on the sidewall of the second supporting layer and a surface

Assignees

• Changxin Memory Tech Inc

Inventors

• Tang Yi

Classifications

• H10B12/488

  Word lines · CPC title

• H10B12/482

  Bit lines · CPC title

• H10B12/05

  Making the transistor · CPC title

• H10B12/03

  Making the capacitor or connections thereto · CPC title

• H10D64/011

  of electrodes ohmically coupled to a semiconductor · CPC title