Semiconductor device

Patent metadata

Field	Value
Publication number	US-2022013524-A1
Application number	US-202117158790-A
Country	US
Kind code	A1
Filing date	Jan 26, 2021
Priority date	Jul 7, 2020
Publication date	Jan 13, 2022
Grant date	—

Abstract

According to the disclosure, highly integrated memory cells and a semiconductor device having the same are provided. According to an embodiment, a semiconductor device comprises a plurality of memory cells vertically stacked on a base substrate, each of the plurality of memory cells includes, a bit line vertically oriented from the base substrate, a capacitor horizontally spaced apart from the bit line, an active layer horizontally oriented between the bit line and the capacitor, a word line positioned on at least one of a top surface and bottom surface of the active layer and horizontally extending in a direction crossing the active layer, and a capping layer positioned between the word line and the bit line and including, at least, a low-k material and an air gap.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a plurality of memory cells vertically stacked on a base substrate; each of the plurality of memory cells includes: a bit line vertically oriented from the base substrate; a capacitor horizontally spaced apart from the bit line; an active layer horizontally oriented between the bit line and the capacitor; a word line positioned on at least one of a top surface and bottom surface of the active layer and horizontally extending in a direction crossing the active layer; and a capping layer positioned between the word line and the bit line, and including, at least one of a low-k material and an air gap.

2 . The semiconductor device of claim 1 , wherein the capping layer is horizontally oriented between the bit line and the word line.

3 . The semiconductor device of claim 1 , wherein the capping layer includes:
a first liner material between the bit line and the word line; and a second liner material surrounded by the first liner material and including the low-k material.

4 . The semiconductor device of claim 3 , wherein the low-k material includes a material with an etch selectivity to the first liner material.

5 . The semiconductor device of claim 3 , wherein the low-k material includes a carbon-doped material, and wherein the first liner material includes silicon oxide or silicon nitride.

6 . The semiconductor device of claim 3 , wherein the low-k material includes silicon carbide (SiC), silicon carbon nitride (SiCN), or silicon carbon oxide (SiCO).

7 . The semiconductor device of claim 1 , wherein the air gap is physically spaced apart from the word line and is embedded in the capping layer.

8 . The semiconductor device of claim 7 , wherein the air gap directly contacts the bit line.

9 . The semiconductor device of claim 1 , wherein the base substrate includes a peripheral circuit unit connected to the bit line.

10 . The semiconductor device of claim 1 , wherein the bit line is part of the active layer, and the capacitor is part of a dynamic random access memory (DRAM) cell array.

11 . The semiconductor device of claim 1 , wherein the capacitor includes:
a storage node horizontally oriented and connected to the active layer; a dielectric layer on the storage node; and a plate node on the dielectric layer, and wherein the storage node is shaped as a cylinder.

12 . The semiconductor device of claim 1 , wherein the word line includes:
an upper word line positioned on the top surface of the active layer; and a lower word line positioned under the bottom surface of the active layer, and wherein different potentials are applied to the upper word line and the lower word line.

13 . The semiconductor device of claim 1 , wherein the word line includes a single word line positioned on the top surface of the active layer, and wherein
the semiconductor device further comprises an insulation layer facing the single word line and positioned under the bottom surface of the active layer.

14 . The semiconductor device of claim 1 , wherein the word line includes a gate-all-around structure to surround the active layer, and wherein the word line with the gate-all-around structure is elongated in a direction crossing the active layer.

15 . The semiconductor device of claim 1 , wherein the memory cells are vertically stacked upwards from the base substrate.

16 . The semiconductor device of claim 1 , wherein the memory cells are vertically stacked downwards from the base substrate.

17 . The semiconductor device of claim 1 , further comprising:
a vertical support supporting the active layers of the memory cells along a direction in which the memory cells are stacked; and a horizontal support positioned between the memory cells along the direction in which the memory cells are stacked.

18 . The semiconductor device of claim 1 , wherein the word line includes:
a body portion elongated in a direction crossing the active layer; and an extension portion horizontally protruding to the capping layer from both side surfaces of the body portion.

19 . The semiconductor device of claim 1 , comprising a three-dimensional (3D) array of the memory cells.

20 . The semiconductor device of claim 1 , wherein the capping layer includes:
a first liner material including the low-k material positioned between the bit line and the word line; and a second liner material surrounded by the first liner material and including the air gap which is embedded.

21 . The semiconductor device of claim 20 , wherein the low-k material includes a carbon-containing material, and the second liner material includes silicon oxide or silicon nitride.

22 . The semiconductor device of claim 20 , wherein the low-k material includes silicon carbide (SiC), silicon carbon nitride (SiCN), or silicon carbon oxide (SiCO).

23 . A semiconductor device, comprising:
a base substrate including a peripheral circuit unit; a bit line vertically oriented from the base substrate; a word line spaced apart from the bit line and the base substrate and horizontally extending in a direction crossing the bit line; and a capping layer including an air gap positioned between the word line and the bit line.

24 . The semiconductor device of claim 23 , wherein the capping layer includes a low-k material.

25 . The semiconductor device of claim 23 , wherein the capping layer includes carbon-doped silicon oxide or carbon-doped silicon nitride.

26 . The semiconductor device of claim 23 , wherein the capping layer includes:
a first liner material positioned between the bit line and the word line; and a second liner material including the air gap, wherein the first liner material is shaped to surround a portion of the second liner material.

27 . The semiconductor device of claim 26 , wherein the second liner material contacts the bit line but does not contact the word line.

28 . The semiconductor device of claim 26 , wherein the second liner material includes a carbon-containing material with a low dielectric constant, and wherein the first liner material includes silicon oxide or silicon nitride.

29 . The semiconductor device of claim 26 , wherein the second liner material includes silicon carbide (SiC), silicon carbon nitride (SiCN), or silicon carbon oxide (SiCO).

Assignees

• Sk Hynix Inc

Inventors

• Ryu Seung Wook
• Son Sung Hun
• Lee Ki Hong

Classifications

• H10W20/48

  Insulating materials thereof · CPC title

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title

• H10D86/80

  characterised by multiple passive components, e.g. resistors, capacitors or inductors · CPC title

• H10D30/6728

  Vertical TFTs · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title