Power module

Patent metadata

Field	Value
Publication number	US-12593739-B2
Application number	US-202118014723-A
Country	US
Kind code	B2
Filing date	Jul 1, 2021
Priority date	Jul 6, 2020
Publication date	Mar 31, 2026
Grant date	Mar 31, 2026

Abstract

The present invention relates to a power module comprising: a lower ceramic substrate ( 200 ); an upper ceramic substrate ( 300 ) which is disposed above the lower ceramic substrate ( 200 ) and has a semiconductor chip (G) mounted on the lower surface thereof; a PCB substrate ( 400 ) disposed above the upper ceramic substrate ( 300 ); and a connection pin ( 800 ) which extends through through holes ( 320 and 420 ) formed in the upper ceramic substrate ( 300 ) and the PCB substrate ( 400 ), and vertically connects electrode patterns (a, b, c, and d) formed on the upper ceramic substrate ( 300 ) and the PCB substrate ( 400 ). The present invention provides a shortened electrical connection distance between the upper ceramic substrate and the PCB substrate, and thus can minimize a current path and enhance the moving efficiency of a high-speed current.

First claim

The invention claimed is:

1 . A power module comprising:
a lower ceramic substrate; an upper ceramic substrate disposed over the lower ceramic substrate and configured to have a semiconductor chip mounted in a flip chip form on a lower surface of the upper ceramic substrate; a PCB substrate disposed over the upper ceramic substrate; a plurality of through holes formed to correspond to the upper ceramic substrate and the PCB substrate; and a connection pin formed in the through hole of the upper ceramic substrate and the through hole of the PCB substrate in a way to penetrate through the through holes and configured to perpendicularly connect an electrode pattern of the upper ceramic substrate and an electrode pattern of the PCB substrate; wherein the connection pin formed in the through hole in a way to penetrate through the through holes is bonded to the electrode pattern of the upper ceramic substrate at an edge of the through hole by laser welding, further comprising a solder layer coated on the electrode pattern at the edge of the through hole of the upper ceramic substrate, melted upon the laser welding, and configured to bond the connection pin to the electrode pattern at the edge of the through hole of the upper ceramic substrate.

2 . The power module of claim 1 , wherein the upper ceramic substrate comprises:
a ceramic base; electrode patterns formed on upper and lower surfaces of the ceramic base; a plurality of via holes formed to penetrate the upper ceramic substrate or the ceramic base up and down; and a metal filler filled into the via hole and configured to connect the electrode patterns of the upper and lower surfaces of the ceramic base.

3 . The power module of claim 2 , wherein the via hole has a diameter of 0.05 mm to 0.3 mm.

4 . The power module of claim 2 , wherein the metal filler is made of one of Ag alloy series, Ag—Pd series, Ag-ceramic series, and Cu alloy series, or a mixed paste of them.

5 . The power module of claim 2 , wherein the via hole is uniformly distributed on an entire surface of the upper ceramic substrate or the ceramic base.

6 . The power module of claim 1 , further comprising a heat sink soldering-bonded to a lower surface of the lower ceramic substrate.

7 . The power module of claim 1 , wherein each of the upper ceramic substrate and the lower ceramic substrate is one of an active metal brazing (AMB) substrate, a direct bonding copper (DBC) substrate, a direct brazed aluminum (DBA) substrate, and a thick printing copper (TPC) substrate.

8 . The power module of claim 1 , further comprising a housing configured to have an empty space, opened up and down, formed at a center thereof and formed of an injection material,
wherein the lower ceramic substrate, the upper ceramic substrate, and the PCB substrate are sequentially installed in the empty space of the housing.

9 . The power module of claim 1 , further comprising a spacer disposed between the lower ceramic substrate and the upper ceramic substrate in a plural number and configured to regulate an isolation distance between the lower ceramic substrate and the upper ceramic substrate.

10 . The power module of claim 1 , wherein:
the upper ceramic substrate comprises a ceramic base and a metal layer that forms an electrode pattern by being bonded to at least one surface of the ceramic base, a curvature inclined part is formed at an edge of the metal layer, and the curvature inclined part protrudes in a direction of an outer circumference of the ceramic base.

11 . The power module of claim 10 , wherein:
the curvature inclined part is formed in a concave shape in a direction of the ceramic base, and a protruded length of the curvature inclined part is increased toward the direction of the ceramic base.

12 . The power module of claim 10 , wherein the curvature inclined part has a multi-stage structure in which a plurality of concave parts is formed and a protruded part is formed at a part where the concave part and the concave part are met.

13 . The power module of claim 12 , wherein the protruded part has a pointed shape.

14 . The power module of claim 10 , wherein the curvature inclined part has a two-stage structure in which two concave parts are formed and a protruded part is formed at a part where the concave part and the concave part are met.

15 . The power module of claim 10 , wherein the curvature inclined part formed at the edge of the metal layer has a mixed structure of a one-stage structure formed in a concave shape in the direction of the ceramic base and a multi-stage structure in which two or more concave parts have been formed in the direction of the ceramic base.

16 . The power module of claim 15 , wherein the curvature inclined part is formed by disposing a photomask on one surface of the metal layer and etching the metal layer exposed by the photomask.

17 . The power module of claim 15 , wherein the curvature inclined part of the multi-stage structure is formed by disposing, on the one surface of the metal layer, a photomask in which two or more holes have been adjacently formed and etching the metal layer exposed by the photomask.

Assignees

• Amosense Co Ltd

Inventors

• Yeo Intae
• Cho Taeho
• Bin Jinhyuck
• Park Seunggon
• Na Wonsan
• Kim Taejung
• Lee Jihyung

Classifications

• H10W40/255

  having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title