Power module packaging with double sided planar interconnection and heat exchangers
US-9041183-B2 · May 26, 2015 · US
Power module with double-sided cooling
US9922911B1 · US · B1
| Field | Value |
|---|---|
| Publication number | US-9922911-B1 |
| Application number | US-201715599688-A |
| Country | US |
| Kind code | B1 |
| Filing date | May 19, 2017 |
| Priority date | Nov 9, 2016 |
| Publication date | Mar 20, 2018 |
| Grant date | Mar 20, 2018 |
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- Title
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Abstract
Official abstract text for this publication.
Disclosed is a power module with double-sided cooling, comprising a semiconductor chip disposed between an upper substrate and a lower substrate; a first power lead disposed between the upper substrate and the semiconductor chip; a signal lead disposed between the upper substrate and the semiconductor chip, and spaced apart from the first power lead; a second power lead disposed between the lower substrate and the semiconductor chip; and a separation plate disposed between the first power lead, the signal lead, and the semiconductor chip; wherein the separation plate connects the first power lead with the semiconductor chip via a first hole formed through the separation plate, and connects the signal lead and the semiconductor chip via a second hole formed through the separation plate.
First claim
Opening claim text (preview).
What is claimed is: 1. A power module with double-sided cooling, comprising: a semiconductor chip disposed between an upper substrate and a lower substrate; a first power lead disposed between the upper substrate and the semiconductor chip; a signal lead disposed between the upper substrate and the semiconductor chip, and spaced apart from the first power lead; a second power lead disposed between the lower substrate and the semiconductor chip; and a separation plate disposed between the first power lead, the signal lead, and the semiconductor chip, wherein the separation plate connects the first power lead with the semiconductor chip via a first hole formed through the separation plate, and connects the signal lead and the semiconductor chip via a second hole formed through the separation plate. 2. The power module of claim 1 , wherein an inner circumferential surface of the second hole disposed in the separation plate is coated with a conductive layer. 3. The power module of claim 1 , wherein the first hole provided in the separation plate is filled with a solder material to connect the first and second power leads with the semiconductor chip. 4. The power module of claim 1 , wherein the separation plate has a thickness of from about 100 to about 200 μm. 5. The power module of claim 1 , wherein the separation plate is made of a dielectric material or a ceramic material. 6. The power module of claim 2 , wherein the conductive layer is a copper plating layer. 7. The power module of claim 2 , wherein the conductive layer has a thickness of from about 1 to about 10 μm. 8. The power module of claim 2 , wherein the conductive layer extends from the inner circumferential surface of the second hole to a top surface of the separation plate. 9. The power module of claim 2 , wherein a lower portion of the second hole disposed in the separation plate is filled with a solder material to connect the conductive layer with the semiconductor chip.
Assignees
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Classifications
between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title
Assembling together parts thereof · CPC title
for devices being provided for in groups H10D8/00 - H10D48/00 · CPC title
having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates · CPC title
Die-attach connectors and bond wires · CPC title
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- What does patent US9922911B1 cover?
- Disclosed is a power module with double-sided cooling, comprising a semiconductor chip disposed between an upper substrate and a lower substrate; a first power lead disposed between the upper substrate and the semiconductor chip; a signal lead disposed between the upper substrate and the semiconductor chip, and spaced apart from the first power lead; a second power lead disposed between the low…
- Who is the assignee on this patent?
- Hyundai Motor Co Ltd, Kia Motors Corp
- What technology area does this patent fall under?
- Primary CPC classification H10W40/778. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 20 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).