Multi-state ferroelectric-RAM with stacked capacitors

Patent metadata

Field	Value
Publication number	US-12593457-B2
Application number	US-202217938667-A
Country	US
Kind code	B2
Filing date	Oct 6, 2022
Priority date	Oct 6, 2022
Publication date	Mar 31, 2026
Grant date	Mar 31, 2026

Abstract

A memory device includes a substrate and vertically stacked ferroelectric capacitors formed on the substrate. A first ferroelectric capacitor has a different capacitive output than a second ferroelectric capacitor when a constant voltage is applied. First and second electrodes are in electrical contact with the vertically stacked ferroelectric capacitors. In some instances, a first capacitor plate in the first ferroelectric capacitor and a second capacitor plate in the second ferroelectric capacitor have different thicknesses. The different thicknesses allow the capacitive output for each capacitor to produce different electric field outputs. Accordingly, a combination of different output signals can be produced based on different threshold voltage levels for each capacitor contributing to the output.

First claim

What is claimed is:

1 . A memory device, comprising:
a substrate; a plurality of vertically stacked ferroelectric capacitors formed on the substrate, wherein
a first ferroelectric capacitor of the plurality of vertically stacked ferroelectric capacitors has a capacitive output that is different from that of a second ferroelectric capacitor of the plurality of vertically stacked ferroelectric capacitors, in response to an applied constant voltage;
a dielectric mandrel positioned between layers of the plurality of vertically stacked ferroelectric capacitors; a first electrode in electrical contact with the plurality of vertically stacked ferroelectric capacitors; and a second electrode in electrical contact with the plurality of vertically stacked ferroelectric capacitors.

2 . The memory device of claim 1 , further comprising:
a first capacitor plate and a second capacitor plate in the first ferroelectric capacitor; and a third capacitor plate and a fourth capacitor plate in the second ferroelectric capacitor, wherein a distance between the first capacitor plate and the second capacitor plate is different from a distance between the third capacitor plate and the fourth capacitor plate.

3 . The memory device of claim 2 , wherein the distance between the first capacitor plate and the second capacitor plate is longer than the distance between the third capacitor plate and the fourth capacitor plate.

4 . The memory device of claim 3 , wherein the first ferroelectric capacitor is positioned on top of the second ferroelectric capacitor.

5 . The memory device of claim 1 , wherein the first electrode is wrapped around the dielectric mandrel and is in contact with a first surface of the plurality of vertically stacked ferroelectric capacitors.

6 . The memory device of claim 5 , wherein the second electrode is in contact with a second surface of the plurality of vertically stacked ferroelectric capacitors.

7 . The memory device of claim 1 , further comprising an isolation layer positioned on top of the substrate and under the plurality of vertically stacked ferroelectric capacitors.

8 . The memory device of claim 7 , wherein the isolation layer extends horizontally under the first electrode and under the second electrode.

9 . The memory device of claim 1 , further comprising a first capacitor plate in the first ferroelectric capacitor and a second capacitor plate in the second ferroelectric capacitor, wherein the first capacitor plate has a thickness that is different from a thickness of the second capacitor plate.

10 . The memory device of claim 1 , wherein the first ferroelectric capacitor has an applied threshold voltage for polarization reversal that is higher or lower than an applied threshold voltage of the second ferroelectric capacitor.

11 . A programmable memory device, comprising:
a plurality of ferroelectric capacitor plate pairs stacked in layers, wherein a thickness of a first capacitor plate pair of the plurality of ferroelectric capacitor plate pairs varies from a thickness of a second capacitor plate pair of the plurality of ferroelectric capacitor plate pairs; one or more isolation layers positioned between the plurality of ferroelectric capacitor plate pairs; a first electrode in contact with the plurality of ferroelectric capacitor plate pairs; and a second electrode in contact with the plurality of ferroelectric capacitor plate pairs.

12 . The programmable memory device of claim 11 , further comprising a dielectric mandrel positioned between the layers of the plurality of ferroelectric capacitor plate pairs.

13 . The programmable memory device of claim 12 , wherein the first electrode is wrapped around the dielectric mandrel and is in contact with a first surface of the plurality of ferroelectric capacitor plate pairs.

14 . The programmable memory device of claim 13 , wherein the second electrode is in contact with a second surface of the plurality of ferroelectric capacitor plate pairs.

15 . The programmable memory device of claim 11 , wherein a distance between the first capacitor plate pair is different from a distance between the second capacitor plate pair.

16 . The programmable memory device of claim 15 , wherein the distance between the first capacitor plate pair is longer than the distance between the second capacitor plate pair.

Assignees

• IBM

Inventors

• Frougier Julien
• Cheng Kangguo
• Xie Ruilong
• Park Chanro
• Sung Min Gyu

Classifications

• H10D62/10

  Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies · CPC title

• H10B53/30 Primary

  characterised by the memory core region · CPC title