Ferroelectric memory device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10453514-B2
Application number	US-201715858056-A
Country	US
Kind code	B2
Filing date	Dec 29, 2017
Priority date	Mar 21, 2017
Publication date	Oct 22, 2019
Grant date	Oct 22, 2019

Abstract

A ferroelectric memory device according to an embodiment includes a substrate, a ferroelectric gate insulation layer disposed along an inner wall of a trench formed in the substrate, and a gate electrode layer disposed on the ferroelectric gate insulation layer. The ferroelectric gate insulation layer has a variable thickness on the inner wall of the trench.

First claim

What is claimed is:

1. A ferroelectric memory device comprising:
a substrate;
an interfacial insulation layer disposed along an inner wall of a trench formed in the substrate;
a ferroelectric gate insulation layer disposed on the interfacial insulation layer; and
a gate electrode layer disposed on the ferroelectric gate insulation layer,
wherein the interfacial insulation layer has a substantially uniform thickness and the ferroelectric gate insulation layer has a variable thickness on the interfacial insulation layer,
wherein, when a predetermined write voltage is applied to the gate electrode layer, the ferroelectric gate insulation layer has a first region in which a first electric field corresponding to a minimum thickness of the ferroelectric insulation layer is formed, a second region in which a second electric filed corresponding to a maximum thickness of the ferroelectric insulation layer is formed, and a third region in which a third electric field that is greater in magnitude than the first electric field and lower in magnitude than the second electric field is formed.

2. The ferroelectric memory device of claim 1 , wherein the ferroelectric gate insulation layer has a ferroelectric characteristic along the same hysteresis loop over the first to third regions.

3. The ferroelectric memory device of claim 2 , wherein,
when an absolute value of the first electric field is less than an absolute value of a coercive electric field of the ferroelectric gate insulation layer, a polarization orientation of the ferroelectric gate insulation layer is not changed by the write voltage;
wherein when the absolute value of the first electric field is equal to or greater than the absolute value of the coercive electric field of the ferroelectric gate insulation layer and the absolute value of the second electric field is less than the absolute value of the coercive electric field of the ferroelectric gate insulation layer, the polarization orientation of the first region and at least a portion of the third region is changed by the write voltage; and
wherein when the absolute value of the second electric field is equal to or greater than the absolute value of the coercive electric field of the ferroelectric gate insulation layer, the polarization orientation of the first region, second region, and third region is changed by the write voltage.

4. The ferroelectric memory device of claim 3 , wherein, when the predetermined write voltage corresponds to an electric field in a range between the absolute value of the first electric field and the absolute value of the second electric field, the write voltage controls a size of a portion of the third region where the polarization orientation is changed.

5. The ferroelectric memory device of claim 1 , wherein the substrate comprises a doped semiconductor material.

6. The ferroelectric memory device of claim 1 , wherein the ferroelectric gate insulation layer comprises at least one oxide among a hafnium oxide, a zirconium oxide, and a hafnium zirconium oxide.

7. The ferroelectric memory device of claim 6 , wherein the ferroelectric gate insulation layer comprises at least one dopant selected from carbon (C), silicon (Si), magnesium (Mg), aluminum (Al), yttrium (Y), nitrogen (N), germanium (Ge), tin (Sn), strontium (Sr), lead (Pb), calcium (Ca), barium (Ba), titanium (Ti), zirconium (Zr), gadolinium (Gd), and lanthanum (La).

8. The ferroelectric memory device of claim 1 , wherein the gate electrode layer comprises at least one selected from tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), platinum (Pt), iridium (Ir), ruthenium (Ru), a tungsten nitride, a titanium nitride, a tantalum nitride, an iridium oxide, a ruthenium oxide, a tungsten carbide, a titanium carbide, a tungsten silicide, a titanium silicide, and a tantalum silicide.

9. The ferroelectric memory device of claim 1 , further comprising
an interfacial insulation layer disposed between the inner wall of the trench and the ferroelectric gate insulation layer.

10. The ferroelectric memory device of claim 1 , further comprising
source and drain regions disposed in the substrate at both ends of the trench.

Assignees

• Sk Hynix Inc

Inventors

• Yoo Hyangkeun

Classifications

• H10D30/0415

  of FETs having ferroelectric gate insulators · CPC title

• H10D30/701

  IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs · CPC title

• G11C11/4074

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title

• G11C11/223 Primary

  using MOS with ferroelectric gate insulating film · CPC title

• H01L27/1159

  Electricity · mapped topic