Control gate structures in three-dimensional memory devices and methods for forming the same

Patent metadata

Field	Value
Publication number	US-12593445-B2
Application number	US-202217861571-A
Country	US
Kind code	B2
Filing date	Jul 11, 2022
Priority date	Jul 11, 2022
Publication date	Mar 31, 2026
Grant date	Mar 31, 2026

Abstract

A method for forming a three-dimensional memory device can include forming a staircase structure. An alternating layer stack is disposed and etched to form steps. A continuous layer disposed on the staircase structure continuously extends over the steps. An insulating layer is disposed on the continuous layer and a slit is formed extending through the staircase structure. The slit exposes sidewalls of the continuous layer and the steps. The sacrificial layer is removed and a cavity is formed in place of the continuous layer. An etch stop layer is disposed in the cavity and continuously extends over the steps. Openings are formed through the insulating layer and expose a portion of a lateral surface of the etch stop layer. The openings are extended through the etch stop layer to expose a lateral surface of each step of the steps. Contacts are formed in the openings.

First claim

What is claimed is:

1 . A method for forming a three-dimensional (3D) memory device, comprising:
forming a staircase structure by etching an alternating layer stack; disposing a continuous layer on the staircase structure; disposing an insulating layer on the continuous layer; removing the continuous layer to form a cavity in place of the continuous layer; disposing an etch stop layer in the cavity, wherein the etch stop layer continuously extends over the staircase structure; forming a plurality of openings through the insulating layer and the etch stop layer, wherein each of the plurality of openings exposes a corresponding step of the staircase structure; and forming a plurality of contacts in the plurality of openings.

2 . The method of claim 1 , further comprising disposing the alternating layer stack by disposing first dielectric layers and second dielectric layers in an alternating manner.

3 . The method of claim 2 , further comprising:
when removing the continuous layer, simultaneously removing the second dielectric layers to form a plurality of additional cavities; and disposing a gate dielectric layer and one or more conductive layers in the plurality of additional cavities.

4 . The method of claim 1 , wherein forming the plurality of openings comprises:
forming the plurality of openings through the insulating layer, wherein each of the plurality of openings exposes a portion of the etch stop layer; and extending the plurality of openings through the etch stop layer.

5 . The method of claim 1 , further comprising:
disposing a gate dielectric layer and one or more conductive layers in the cavity; and removing the one or more conductive layers from the cavity.

6 . The method of claim 1 , further comprising oxidizing the etch stop layer through the plurality of openings.

7 . The method of claim 1 , wherein disposing the etch stop layer comprises disposing a metal silicide material or a silicon nitride material.

8 . The method of claim 1 , wherein exposing the corresponding step of the staircase structure comprises exposing a lateral surface of the each step of a plurality of steps of the staircase structure by etching through a gate dielectric layer and exposing an underlying conductive material.

9 . The method of claim 1 , further comprising:
after disposing the insulating layer and before removing the continuous layer, forming a plurality of dummy channels through the insulating layer, the continuous layer, and the staircase structure.

10 . The method of claim 1 , further comprising:
before disposing the continuous layer, forming a liner layer on the staircase structure.

11 . A method for forming a three-dimensional (3D) memory device, comprising:
disposing an alternating layer stack on a substrate, comprising disposing a plurality of first dielectric layers and a plurality of second dielectric layers in an alternating manner; etching the alternating layer stack to form a staircase structure; disposing a third dielectric layer on the staircase structure; disposing an insulating layer on the third dielectric layer; removing, the plurality of second dielectric layers to form a plurality of cavities, and the third dielectric layer to form an additional cavity; disposing a gate dielectric layer and one or more conductive layers in each cavity of the plurality of cavities and in the additional cavity; removing the one or more conductive layers from the additional cavity and disposing an etch stop layer in the additional cavity; forming a plurality of openings through the insulating layer, wherein each opening of the plurality of openings terminates at the etch stop layer; etching the etch stop layer through the plurality of openings to expose portions of the one or more conductive layers disposed in the each cavity of the plurality of cavities; and forming a plurality of contacts on the exposed portions of the one or more conductive layers.

12 . The method of claim 11 , wherein:
the staircase structure comprises a plurality of steps; each step of the plurality of steps comprises a sidewall surface and a lateral surface; and the third dielectric layer continuously contacts sidewall surfaces and lateral surfaces of the plurality of steps.

13 . The method of claim 11 , further comprising oxidizing a portion of the etch stop layer through the plurality of openings.

14 . The method of claim 11 , further comprising forming a slit extending through the staircase structure, wherein the slit exposes sidewalls of the plurality of first dielectric layers, sidewalls of the plurality of second dielectric layers, and a sidewall of the third dielectric layer.

15 . The method of claim 14 , wherein:
removing the plurality of second dielectric layers and the third dielectric layer comprises etching the plurality of second dielectric layers and the third dielectric layer through the slit.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Zhang Kun
• Zhou Wenxi
• Xia Zhiliang
• Huo Zongliang

Classifications

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/10 Primary

  characterised by the top-view layout · CPC title

• H10B41/35

  with a cell select transistor, e.g. NAND · CPC title

• H10B41/10

  characterised by the top-view layout · CPC title