Grain structure engineering for metal gapfill materials

US12588533B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12588533-B2
Application numberUS-202318225286-A
CountryUS
Kind codeB2
Filing dateJul 24, 2023
Priority dateJul 24, 2023
Publication dateMar 24, 2026
Grant dateMar 24, 2026

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method for depositing copper onto a substrate includes grain engineering to control the internal structure of the copper. In some embodiments, the method comprises depositing a grain control layer conformally onto a copper seed layer in a structure on the substrate where the grain control layer is a non-conducting material, etching the grain control layer using a direct deep reactive ion etch (DRIE) process to remove portions of the grain control layer on horizontal surfaces within the structure, and depositing a copper material onto the structure such that at least one grain parameter of the copper material is controlled, at least in part, by a remaining portion of the grain control layer on vertical surfaces of the structure. In some embodiments, the deposited copper material in the structure has a < 111> grain orientation normal to a horizontal surface of the structure.

First claim

Opening claim text (preview).

The invention claimed is: 1 . A method for controlling gapfill material deposition processes, comprising: depositing a metal seed layer conformally onto a substrate with at least one structure formed into the substrate; depositing a grain control layer conformally onto the substrate and into the at least one structure, wherein the grain control layer is a non-conducting material; depositing a polymer layer on the substrate in an etch chamber such that at least one exposed corner of the at least one structure is covered during a subsequent etching process; etching the grain control layer using an etch process to remove portions of the grain control layer on horizontal surfaces within the at least one structure; and depositing a metal gapfill material onto the at least one structure such that at least one grain parameter of the metal gapfill material is controlled, at least in part, by a remaining portion of the grain control layer on vertical surfaces of the at least one structure. 2 . The method of claim 1 , wherein the at least one structure includes a trench, a via, or a damascene structure. 3 . The method of claim 1 , wherein the grain control layer is an inorganic dielectric material. 4 . The method of claim 3 , wherein the inorganic dielectric material is SiN, SiO 2 , or SiCN. 5 . The method of claim 1 , wherein the grain control layer is an organic dielectric material. 6 . The method of claim 5 , wherein the organic dielectric material is a fluoropolymer material, a polyimide material, a polybenzoxazole material, or a self-assembled monolayer. 7 . The method of claim 1 , wherein depositing the metal gapfill material onto the at least one structure forms a copper gapfill material in the at least one structure with a < 111 > grain orientation normal to a horizontal surface of the at least one structure. 8 . The method of claim 1 , wherein depositing the metal gapfill material onto the at least one structure forms a copper gapfill material in the at least one structure with a copper grain orientated lengthwise along a length of the at least one structure and wherein the copper grain fills a width of the at least one structure. 9 . The method of claim 1 , wherein the at least one structure on the substrate has sidewalls of 90 degrees or less relative to horizontal surfaces within the at least one structure. 10 . The method of claim 1 , wherein the grain control layer is selected based on adhesion characteristics to the metal seed layer. 11 . The method of claim 1 , wherein the grain control layer has a thickness of approximately 1 nanometer or less. 12 . The method of claim 1 , wherein the at least one structure is a trench or via formed by a lithography process in a photo-imageable organic dielectric material of the substrate. 13 . The method of claim 1 , wherein the method is used in a copper-to-copper hybrid bonding process with a bonding temperature of 250 degrees or less. 14 . The method of claim 1 , wherein the grain control layer remains as part of the at least one structure during subsequent processing of the at least one structure. 15 . The method of claim 1 , wherein the metal gapfill material is deposited using electrochemical plating. 16 . The method of claim 1 , wherein the etch process is a direct deep reactive ion etch (DRIE) process. 17 . A method for depositing copper, comprising: depositing a grain control layer conformally onto a copper seed layer in at least one structure on a substrate, wherein the grain control layer is a non-conducting material; depositing a polymer layer on the substrate in an etch chamber such that at least one exposed corner of the at least one structure is covered during a subsequent etching process; etching the grain control layer using a direct deep reactive ion etch (DRIE) process to remove portions of the grain control layer on horizontal surfaces within the at least one structure; and depositing a copper gapfill material onto the at least one structure such that at least one grain parameter of the copper gapfill material is controlled, at least in part, by a remaining portion of the grain control layer on vertical surfaces of the at least one structure, wherein deposited copper gapfill material in the at least one structure has a < 111 > grain orientation normal to a horizontal surface of the at least one structure. 18 . The method of claim 17 , wherein the grain control layer is an organic dielectric material. 19 . The method of claim 17 , wherein the grain control layer has a thickness of approximately 1 nanometer or less. 20 . A non-transitory, computer readable medium having instructions stored thereon that, when executed, cause a method for depositing copper to be performed, the method comprising: depositing a grain control layer conformally onto a copper seed layer in at least one structure on a substrate, wherein the grain control layer is a non-conducting material; depositing a polymer layer on the substrate in an etch chamber such that at least one exposed corner of the at least one structure is covered during a subsequent etching process; etching the grain control layer using a direct deep reactive ion etch (DRIE) process to remove portions of the grain control layer on horizontal surfaces within the at least one structure; and depositing a copper material onto the at least one structure such that at least one grain parameter of the copper material is controlled, at least in part, by a remaining portion of the grain control layer on vertical surfaces of the at least one structure, wherein deposited copper material in the at least one structure has a < 111 > grain orientation normal to a horizontal surface of the at least one structure.

Assignees

Inventors

Classifications

  • characterised by the pads after the direct bonding · CPC title

  • characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

  • relative to the surface, e.g. recessed, protruding · CPC title

  • by etching · CPC title

  • Changing the shapes of bond pads · CPC title

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What does patent US12588533B2 cover?
A method for depositing copper onto a substrate includes grain engineering to control the internal structure of the copper. In some embodiments, the method comprises depositing a grain control layer conformally onto a copper seed layer in a structure on the substrate where the grain control layer is a non-conducting material, etching the grain control layer using a direct deep reactive ion etch…
Who is the assignee on this patent?
Applied Materials Inc
What technology area does this patent fall under?
Primary CPC classification H10W99/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 24 2026 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).