Methods and apparatus for integrating carbon nanofiber into semiconductor devices using W2W fusion bonding

Patent metadata

Field	Value
Publication number	US-12588502-B2
Application number	US-202217728625-A
Country	US
Kind code	B2
Filing date	Apr 25, 2022
Priority date	Apr 25, 2022
Publication date	Mar 24, 2026
Grant date	Mar 24, 2026

Abstract

A semiconductor device assembly that includes carbon nanofibers (CNFs) for heat dissipation has a CNF layer. Molding compound encapsulates the CNF layer to form an encapsulated CNF layer. The molding compound extends between individual adjacent CNFs within the encapsulated CNF layer, and upper edges of at least a portion of individual CNFs within the encapsulated CNF layer are exposed along an upper surface of the encapsulated CNF layer. The upper surface of the CNF layer is removably attached to a bottom surface of a carrier wafer.

First claim

We claim:

1 . A semiconductor device assembly including carbon nanofibers for heat dissipation, comprising:
a carbon nanofiber (CNF) layer; molding compound encapsulating the CNF layer to form an encapsulated CNF layer, the molding compound extending between individual adjacent CNFs within the encapsulated CNF layer; a metal seed layer extending across and in direct contact with a bottom surface of the encapsulated CNF layer; a silicon oxide (SiO) layer extending across and in direct contact with a bottom surface of the metal seed layer; and a plurality of die stacks formed over a device wafer, wherein the plurality of die stacks are encapsulated in second molding compound, wherein upper surfaces of the die stacks and the second molding compound are bonded to the SiO layer.

2 . The semiconductor device assembly of claim 1 , wherein the device wafer and the encapsulated CNF layer are approximately 12 inches or 300 cm in diameter.

3 . The semiconductor device assembly of claim 1 , wherein upper edges of at least a portion of individual CNFs within the encapsulated CNF layer are exposed along an upper surface of the encapsulated CNF layer.

4 . The semiconductor device assembly of claim 1 , wherein each of the plurality of die stacks include an equal number of die.

5 . The semiconductor device assembly of claim 1 , wherein a polymer layer extends between the SiO layer and the upper surfaces of the die stacks and the second molding compound, wherein the polymer layer and the SiO layer are fusion bonded to each other.

6 . The semiconductor device assembly of claim 1 , wherein a polymer layer extends between the SiO layer and the upper surfaces of the die stacks and the second molding compound, wherein the polymer layer and the SiO layer are cold welded to each other.

7 . The semiconductor device assembly of claim 6 , wherein the polymer layer has a thickness that is between about 0.5 and 2.0 microns.

8 . The semiconductor device assembly of claim 1 , wherein the molding compound encapsulating the CNF layer comprises at least one of an epoxy-based liquid compound with granules, an epoxy-based liquid compound without granules, a granular compound, a thin-film based underfill, a thin-film based compound, a resin-based encapsulant, or a polymer.

9 . The semiconductor device assembly of claim 1 , wherein a thickness of the encapsulated CNF layer less than or equal to about 200 microns.

10 . A semiconductor device assembly including carbon nanofibers for heat dissipation, comprising:
a carbon nanofiber (CNF) layer; molding compound encapsulating the CNF layer to form an encapsulated CNF layer, the molding compound extending between individual adjacent CNFs within the encapsulated CNF layer, and wherein upper edges of at least a portion of individual CNFs within the encapsulated CNF layer are exposed along an upper surface of the encapsulated CNF layer; a metal seed layer extending across and in direct contact with a bottom surface of the encapsulated CNF layer; a silicon oxide (SiO) layer extending across a bottom surface of the metal seed layer; and a die stack formed over a memory device, wherein the die stack includes at least two dies that are attached to each other, wherein the die stack is encapsulated in second molding compound, wherein an upper surface of the die stack and the molding compound is bonded to the SiO layer.

11 . The semiconductor device assembly of claim 10 , further comprising a polymer layer extending across the upper surface of the die stack and the molding compound, wherein the polymer layer is further bonded to the SiO layer.

12 . The semiconductor device assembly of claim 11 , wherein the polymer layer is thinner than the encapsulated CNF layer.

13 . The semiconductor device assembly of claim 10 , wherein the bonding between the SiO layer and the die stack is one of cold welding, fusion bonding, oxide to oxide bonding, or dielectric to dielectric bonding.

14 . The semiconductor device assembly of claim 10 , wherein the molding compound encapsulating the CNF layer comprises at least one of an epoxy-based liquid compound with granules, an epoxy-based liquid compound without granules, a granular compound, a thin-film based underfill, a thin-film based compound, a resin-based encapsulant, or a polymer.

Assignees

• Micron Technology Inc

Inventors

• Zhou Wei
• Street Bret K
• Griffin Amy R

Classifications

• H10W72/30

  Die-attach connectors · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10W90/791

  of direct-bonded pads · CPC title

• H10W90/732

  between stacked chips · CPC title