Integrated circuit heat spreader including sealant interface material

Patent metadata

Field	Value
Publication number	US-12588499-B2
Application number	US-202016905731-A
Country	US
Kind code	B2
Filing date	Jun 18, 2020
Priority date	Jun 18, 2020
Publication date	Mar 24, 2026
Grant date	Mar 24, 2026

Abstract

A hybrid integrated heat spreader suitable for an integrated circuit (IC) die package. The hybrid integrated heat spreader includes a top sheet material and a sealant interface material located where the heat spreader is to contact an assembly substrate. The sealant interface material may offer greater adhesion to a sealant employed between the interface material and the package substrate. In some examples, the sealant interface material has a greater surface roughness and/or a different composition than a surface of the integrated heat spreader that is in close thermal contact with an IC die through a thermal interface material. With the sealant interface material improving adhesion, the sealant may have a higher bulk modulus, enabling the integrated heat spreader to impart greater stiffness to the IC die package assembly.

First claim

What is claimed is:

1 . An integrated circuit (IC) die package heat spreader, comprising:
a top sheet having an interior surface area that is to be over an IC die, the top sheet comprising a metal surface finish covering an underlying material, wherein the metal surface finish has an RMS surface roughness of less than 1 μm; and an interface material on a periphery of the top sheet, wherein the interface material substantially encloses the interior surface area and is absent from the interior surface area, and wherein the interface material has a different composition than the metal surface finish, and wherein the interface material has an RMS surface roughness of at least 10 μm.

2 . The IC die package heat spreader of claim 1 , wherein:
the interface material has a thickness of no more than 250 μm, and a transverse width of no more than 5 mm; and the interior surface area exceeds 10 mm 2 .

3 . The IC die package heat spreader of claim 1 , wherein the interface material comprises two or more ridges of the interface material, and wherein the metal surface finish is exposed within a space between the ridges of the interface material.

4 . The IC die package heat spreader of claim 1 , wherein:
the metal surface finish is a first metal or metal alloy; and the interface material is a second metal or metal alloy.

5 . The IC die package heat spreader of claim 1 , wherein the metal surface finish comprises Ni and the interface material comprises at least one of Au, Ag, Cu, Ti, W, Al, Fe, Cr, Mo, Si, or C.

6 . The IC die package heat spreader of claim 1 , wherein the top sheet further comprises a bulk metal underlying the metal surface finish, and wherein the metal surface finish is between the bulk metal and the interface material.

7 . The IC die package heat spreader of claim 6 , wherein the bulk metal comprises Cu.

8 . The IC die package heat spreader of claim 6 , wherein the interface material comprises at least one of Cu or Al.

9 . The IC die package heat spreader of claim 1 , wherein the interior surface area is within an interior cavity of the top sheet surrounded by a sidewall comprising the metal surface finish, and wherein the interface material is on bottom surface of the sidewall in a plane substantially parallel to a plane of the interior surface area.

10 . The IC die package heat spreader of claim 9 , wherein the metal surface finish is on an exterior surface of the top sheet, opposite the interior surface area, and wherein the interface material is in contact with the the metal surface finish.

11 . An integrated circuit (IC) die package, comprising:
a package substrate; an IC die coupled to a first region of the package substrate; and the IC die package heat spreader of claim 1 , wherein the interior surface area is over the IC die coupled to the first region of the package substrate.

12 . The IC die package heat spreader of claim 1 , wherein the interface material has a void area ranging from 0.1% to 0.5%.

13 . The IC die package of claim 11 , further comprising an adhesive sealant in contact with the interface material and with a second region of the package substrate that substantially surrounds the first region.

14 . The IC die package of claim 13 , wherein the adhesive sealant has a bulk modulus of more than 85 Shore A.

15 . The IC die package of claim 14 , wherein:
the adhesive sealant comprises an epoxy resin; the surface finish has an RMS surface roughness less than 10 μm; and a surface of the interface material in contact with the adhesive sealant has a profile roughness of at least 10 μm between a maximum peak and a minimum valley.

16 . The IC die package of claim 11 , further comprising a thermal interface material (TIM) between the IC die and the interior surface.

17 . A computer platform comprising:
a power supply; and the IC die package of claim 11 coupled to the power supply.

18 . An integrated circuit (IC) die package, comprising:
a package substrate; an IC die coupled to a first region of the package substrate; a heat spreader over the IC die, wherein the heat spreader comprises:
a top sheet having an interior surface area that is over the IC die, the top sheet comprising a metal surface finish covering an underlying material; and
an interface material on a periphery of the top sheet, wherein the interface material substantially encloses the interior surface area and is absent from the interior surface area, wherein the interface material has a different composition than the surface finish, wherein a surface roughness is greater for the interface material than the for surface finish, and wherein the interface material has a surface roughness profile with peaks and valleys varying between a minimum surface profile valley and a maximum surface profile peak that differ by at least 10 μm in a direction normal to a plane of the top sheet; and
an adhesive sealant in contact with the interface material and in contact with a second region of the package substrate that substantially surrounds the first region.

19 . The IC die package of claim 18 , wherein the adhesive sealant has a bulk modulus of more than 85 Shore A.

Assignees

• Intel Corp

Inventors

• Eid Feras
• Chan Arguedas Sergio Antonio
• Falola Bamidele Daniel

Classifications

• H10W74/127

  characterised by arrangements for sealing or adhesion · CPC title

• H10W74/124

  the encapsulations having cavities other than that occupied by chips · CPC title

• H10W40/258

  Metallic materials (H10W40/254, H10W40/257, H10W40/255, H10W40/251, H10W40/253 take precedence) · CPC title

• H10W40/037

  Assembling together parts thereof · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title