Integrated circuit devices including stacked elements and methods of forming the same

Patent metadata

Field	Value
Publication number	US-12588489-B2
Application number	US-202217738393-A
Country	US
Kind code	B2
Filing date	May 6, 2022
Priority date	Feb 25, 2022
Publication date	Mar 24, 2026
Grant date	Mar 24, 2026

Abstract

Integrated circuit devices may include a transistor, a passive device, a substrate extending between the transistor and the passive device and a power rail. The passive device may be spaced apart from the substrate. Each of the passive device and the power rail may have a first surface facing the substrate, and the first surface of the passive device is closer than the first surface of the power rail to the substrate.

First claim

What is claimed is:

1 . A method of forming an integrated circuit device, the method comprising:
providing a first structure and a second structure, wherein the first structure comprises a transistor, a first bonding pad on a first side of the first structure, a first substrate extending between the transistor and the first bonding pad, and the second structure comprising a second substrate, a second bonding pad on a first side of the second structure, and a second contact plug; forming a back-end metal structure on a second side of the first structure that is opposite the first side thereof; forming a portion of a passive device in the second substrate; attaching the first side of the first structure to the first side of the second structure, wherein, after attaching the first side of the first structure to the first side of the second structure, the first bonding pad contacts the second bonding pad; and then forming a power rail on a second side of the second structure that is opposite the first side thereof, wherein the second substrate extends between the first bonding pad and the power rail, and the second contact plug electrically connects the second bonding pad to the power rail.

2 . The method of claim 1 , wherein the first structure further comprises a first contact plug that extends through the first substrate and is electrically connected to the portion of the passive device.

3 . The method of claim 1 , wherein the second substrate is spaced apart from the first substrate in a first direction, wherein the integrated circuit device further comprises a first contact plug that extends through the first substrate from the first bonding pad on the first side of the first structure toward the second side of the first structure and is electrically connected to a source/drain region of the transistor,
the first contact plug comprises a surface that is coplanar with a surface of the first substrate and contacts a surface of the first bonding pad, and a width of the surface of the first bonding pad in a second direction is wider than a width of the surface of the first contact plug in the second direction, and the second direction is perpendicular to the first direction.

4 . The method of claim 3 , wherein the second contact plug extends through the second substrate from the second bonding pad on the first side of the second structure to the power rail on the second side of the second structure and is electrically connected to the first contact plug, wherein the second contact plug comprises a surface that is coplanar with a surface of the second substrate.

5 . The method of claim 1 , wherein the second substrate is spaced apart from the first substrate in a first direction, wherein the integrated circuit device further comprises a first contact plug that extends through the first substrate and is electrically connected to a source/drain region of the transistor, and wherein the second contact plug extends through the second substrate and is electrically connected to the first contact plug,
wherein the first bonding pad is a portion of a first merged bonding pad that contacts both the first contact plug and the second contact plug, and a width of the first merged bonding pad in a second direction increases and then decreases as a distance from the first substrate increases, and the second direction is perpendicular to the first direction.

6 . The method of claim 5 , wherein the integrated circuit device further comprises a first etch stop layer on the first substrate, a second etch stop layer between the first etch stop layer and the second substrate, and a bonding insulator extending between the first etch stop layer and the second etch stop layer,
wherein the first merged bonding pad extends through the first etch stop layer, the bonding insulator and the second etch stop layer.

7 . The method of claim 1 , wherein the integrated circuit device further comprises a bonding insulator extending between the first substrate and the second substrate, and an etch stop layer extending between the bonding insulator and the second substrate,
wherein the first bonding pad is a portion of a first merged bonding pad, and the second bonding pad is a portion of the first merged bonding pad, and the first merged bonding pad extends through the bonding insulator and the etch stop layer.

8 . The method of claim 7 , wherein the second substrate is spaced apart from the first substrate in a first direction, wherein a width of the first merged bonding pad in a second direction increases and then decreases as a distance from the first substrate increases, and the second direction is perpendicular to the first direction.

9 . The method of claim 1 , wherein each of the passive device and the power rail comprises a first surface facing the first substrate, and
the first surface of the passive device is closer than the first surface of the power rail to the first substrate.

10 . The method of claim 1 , wherein forming the portion of the passive device in the second substrate is performed before attaching the first structure to the second structure.

11 . The method of claim 1 , wherein forming the portion of the passive device in the second substrate is performed after attaching the first structure to the second structure.

12 . The method of claim 4 , wherein the first and second contact plugs are aligned in the first direction.

13 . The method of claim 1 , wherein the second structure is stacked on the first structure in a first direction, wherein the integrated circuit device comprises a first region including the transistor and a second region including the passive device and spaced apart from the first region in a second direction.

14 . The method of claim 13 , wherein the transistor in the first region is free of overlap with passive devices in the first direction, and the passive device in the second region is free of overlap with transistors in the first direction.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hong Byounghak
• Yim Jeonghyuk
• Hwang Inchan
• Son Gilhwan
• Lee Seungyoung
• Park Saehan
• Lee Janggeun
• Jung Myunghoon
• Yun Seungchan
• Ham Buhyun
• Seo Kang-Ill

Classifications

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10D84/0149

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title