Semiconductor fin structure cut process

Patent metadata

Field	Value
Publication number	US-12588449-B2
Application number	US-202217945292-A
Country	US
Kind code	B2
Filing date	Sep 15, 2022
Priority date	Nov 23, 2021
Publication date	Mar 24, 2026
Grant date	Mar 24, 2026

Abstract

The present application relates to a semiconductor fin structure cut process. The process includes: providing a semiconductor substrate and forming a plurality of fin structures on the semiconductor substrate, a gap being formed between every two adjacent fin structures; depositing a first dielectric layer, the first dielectric layer being filled in the gaps so that all fin structures are connected into a whole to form a semiconductor with fins; forming a plurality of pattern layer strips on the semiconductor with fins, a groove being formed between every two adjacent pattern layer strips, the fin structures closest to each pattern layer strip in the semiconductor with fins being necessary fin structures, attaching mask strips onto side surfaces of each pattern layer strip, the mask strips covering the necessary fin structures; etching the semiconductor with fins so that the unnecessary fin structures not covered by the mask strips are truncated.

First claim

What is claimed is:

1 . A semiconductor fin structure cut process, wherein the semiconductor fin structure cut process comprises the following steps performed sequentially:
providing a semiconductor substrate and forming a plurality of fin structures on the semiconductor substrate, a gap being formed between every two adjacent fin structures; depositing a first dielectric layer, the first dielectric layer being filled in the gaps so that all of the fin structures are connected into a whole to form a semiconductor with fins; forming a plurality of pattern layer strips on the semiconductor with fins, a groove being formed between every two adjacent pattern layer strips, an upper surface of the semiconductor with fins at positions of the grooves being exposed, the fin structures closest to each pattern layer strip in the semiconductor with fins being necessary fin structures, and remaining fin structures being unnecessary fin structures; attaching mask strips onto side surfaces of each pattern layer strip, the mask strips covering the necessary fin structures; and etching the semiconductor with fins on the basis of a pattern formed by the mask strips so that the unnecessary fin structures not covered by the mask strips are truncated.

2 . The semiconductor fin structure cut process according to claim 1 , wherein the depositing the first dielectric layer, the first dielectric layer being filled in the gaps so that all of the fin structures are connected into the whole to form the semiconductor with fins comprises:
depositing the first dielectric layer, the first dielectric layer being filled in the gaps so that all fin structures are connected into a whole; and enabling tops of the fin structures connected into a whole to be covered with the first dielectric layer to form the semiconductor with fins.

3 . The semiconductor fin structure cut process according to claim 2 , wherein after the semiconductor with fins is formed, the semiconductor fin structure cut process further comprises:
performing chemical-mechanical polishing to a surface layer of the fin to planarize the upper surface of the semiconductor with fins.

4 . The semiconductor fin structure cut process according to claim 1 , wherein the attaching the mask strips onto the side surfaces of each pattern layer strip, the mask strips covering the necessary fin structures comprises:
depositing a second dielectric, so that the second dielectric is attached onto bottom surfaces of the grooves and side surfaces and top surfaces of the pattern layer strips to form a second dielectric layer, the second dielectric layer attached onto the side surfaces of the pattern layer strips covering the fin structures closest to the side surfaces of the pattern layer strips; and etching the second dielectric layer to remove second dielectric layer covering the bottom surfaces of the grooves and the top surfaces of the pattern layer strips, a remaining second dielectric layer covering the necessary fin structures to form mask strips.

5 . The semiconductor fin structure cut process according to claim 4 , wherein the depositing the second dielectric comprises:
depositing the second dielectric through silicon oxide atoms at a temperature ranging from 80° C. to 200° C., so that the second dielectric is attached onto the bottom surfaces of the grooves and the side surfaces and the top surfaces of the pattern layer strips to form the second dielectric layer.

6 . The semiconductor fin structure cut process according to claim 1 , wherein the forming the plurality of pattern layer strips on the semiconductor with fins, the groove being formed between every two adjacent pattern layer strips, the upper surface of the semiconductor with fins at the positions of the grooves being exposed comprises:
sequentially forming a hard mask layer, an anti-reflection layer and a photoresist layer on the semiconductor with fins; etching the photoresist layer through a photolithography process so that a remaining photoresist layer forms a first pattern; etching the anti-reflection layer and the hard mask layer on the basis of the photoresist layer with the first pattern, so that the first pattern is transferred into the anti-reflection layer and the hard mask layer; and performing etching to remove the anti-reflection layer with the first pattern and reserve the hard mask layer with the first pattern.

7 . The semiconductor fin structure cut process according to claim 6 , wherein the anti-reflective layer with the first pattern comprises a plurality of the pattern layer strips, and the groove is formed between every two adjacent layer strips.

8 . The semiconductor fin structure cut process according to claim 1 , wherein after the etching the semiconductor with the fins on the basis of the pattern formed by the mask strips so that the unnecessary fin structures not covered by the mask strips are truncated, roots of the unnecessary fin structures are reserved to a height ranging from 18 nm to 22 nm.

9 . The semiconductor fin structure cut process according to claim 1 , wherein after the etching the semiconductor with fins on the basis of the pattern formed by the mask strips so that the unnecessary fin structures not covered by the mask strips are truncated, the semiconductor fin structure cut process further comprises:
forming a third dielectric layer through deposition so that the third dielectric layer is filled in a spacing groove between every two adjacent necessary fin structures.

10 . The semiconductor fin structure cut process according to claim 9 , wherein after the forming the third dielectric layer through deposition so that the third dielectric layer is filled in the spacing groove between every two adjacent necessary fin structures, an upper surface of the third dielectric layer is planarized through chemical-mechanical polishing.

Assignees

• Shanghai Huali Integrated Circuit Corp

Inventors

• Qiu Yanzhan

Classifications

• H10P76/2043

  using an anti-reflective coating · CPC title

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/694

  characterised by their behaviour during the process, e.g. soluble masks or redeposited masks · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/024 Primary

  of fin field-effect transistors [FinFET] · CPC title