FinFET transistor cut etching process method

Patent metadata

Field	Value
Publication number	US-11637194-B2
Application number	US-202016895083-A
Country	US
Kind code	B2
Filing date	Jun 8, 2020
Priority date	Oct 17, 2019
Publication date	Apr 25, 2023
Grant date	Apr 25, 2023

Abstract

The present disclosure discloses a FinFET transistor cut etching process method, comprising: step 1, forming a first photoresist pattern to define a cut etching region of the FinFET transistor; step 2, forming a second amorphous semiconductor pattern; step 3, forming a first dielectric layer and a first groove; step 4, forming a second dielectric layer that fully fills the first groove; step 5, performing CMP using the second amorphous semiconductor layer as a stop layer, so as to form a sidewall and a second dielectric layer strip; step 6, performing self-alignment to remove each side wall; step 7, performing a wet process to remove the amorphous semiconductor strip; and step 8: performing etching by using each second dielectric layer strip as a mask, so as to form a fin and achieve cut etching of the FinFET transistor. The present disclosure can enlarge the process window and reduce the process cost.

First claim

What is claimed is:

1. A FinFET transistor cut etching process method, comprising the following steps:
step 1, providing a semiconductor substrate, the semiconductor substrate having a surface where a first hard mask and a second amorphous semiconductor layer are sequentially formed thereon, and forming a first photoresist pattern by means of a photolithographic process to indirectly define a fin cut etching region of a FinFET transistor, wherein the first photoresist pattern is formed by an arrangement of a plurality of photoresist stripes, the first photoresist pattern directly defines a graphic structure of the second amorphous semiconductor layer, an area covered by first photoresist stripes is a reserved area of the second amorphous semiconductor layer, and an area between the first photoresist stripes is a removed area of the second amorphous semiconductor layer,
the first photoresist pattern is configured to be removed before a subsequent etching of the semiconductor substrate, and the first photoresist pattern is configured to be transferred to the semiconductor substrate after the subsequent etching of the semiconductor substrate, thereby realizing an indirect definition of the fin cut etching region in advance,
the fin cut etching region is located in the semiconductor substrate and corresponds to a stripe region in which a fin is removed, each fin presents a strip structure, and, in a plan view, a subsequently formed fin cut etching region and the fin present an alternate arrangement structure;
step 2, etching the second amorphous semiconductor layer by using the first photoresist pattern as a mask, so as to form a second amorphous semiconductor pattern, wherein the second amorphous semiconductor pattern is formed by an arrangement of a plurality of amorphous semiconductor stripes, and the amorphous semiconductor stripes are defined by the photoresist stripes;
then, removing the first photoresist pattern;
step 3, forming a first dielectric layer, wherein the first dielectric layer covers a top surface and a side surface of the amorphous semiconductor stripe, and a surface of the first hard mask between the amorphous semiconductor stripes, and there is an interval between the first dielectric layers on side surfaces of the amorphous semiconductor stripes and a first groove is formed therefrom;
step 4, forming a second dielectric layer, wherein the second dielectric layer fully fills the first groove and extends onto a surface of the first dielectric layer outside the first groove;
step 5, performing planarization by means of a chemical mechanical polishing process using the second amorphous semiconductor layer as a stop layer, after the planarization, forming a side wall composed of the first dielectric layer on the side surface of the amorphous semiconductor stripe, and forming a second dielectric layer stripe composed of the second dielectric layer filled in the first groove between the side walls, wherein the second dielectric layer stripe defines a corresponding formation region of a fin;
step 6, performing self-alignment by using each amorphous semiconductor stripe and each second dielectric layer stripe as masks, so as to remove each side wall;
step 7, performing a wet process to remove each amorphous semiconductor stripe, taking advantage of a characteristics that materials of the amorphous semiconductor stripe and the first hard mask are different, the materials of the amorphous semiconductor stripe and the first dielectric layer are different, and the materials of amorphous semiconductor stripe and the second dielectric layer are different, all of the amorphous semiconductor stripes are removed, without a need to use photolithography; and
step 8, sequentially etching the first hard mask and the semiconductor substrate by using each second dielectric layer stripe as a mask, so as to form the fin and achieve cut etching of the FinFET transistor to form the fin cut etching region,
a forming area of the fin is the area covered by the second dielectric layer stripe,
the fin cut etching region is located in the area covered by the amorphous semiconductor strip, and
an interval area between the fin and the fin cut etching region is located in the area covered by the side wall.

2. The FinFET transistor cut etching process method according to claim 1 , wherein the semiconductor substrate is a silicon substrate.

3. The FinFET transistor cut etching process method according to claim 2 , wherein a material of the second amorphous semiconductor layer is amorphous silicon.

4. The FinFET transistor cut etching process method according to claim 3 , wherein a material of the first hard mask comprises an oxide layer or a nitride layer.

5. The FinFET transistor cut etching process method according to claim 4 , wherein the first hard mask comprises a third oxide layer, a fourth nitride layer, and a fifth oxide layer which are sequentially stacked.

6. The FinFET transistor cut etching process method according to claim 5 , wherein the first dielectric layer is a nitride layer.

7. The FinFET transistor cut etching process method according to claim 6 , wherein the second dielectric layer is an oxide layer.

8. The FinFET transistor cut etching process method according to claim 1 , wherein, in step 2, the second amorphous semiconductor layer is etched by means of a dry etching process.

9. The FinFET transistor cut etching process method according to claim 1 , wherein, in step 3, a thickness of the first dielectric layer defines an interval between the fin and the fin cut etching region.

10. The FinFET transistor cut etching process method according to claim 9 , wherein, in step 3, the first dielectric layer is grown by means of an atomic layer deposition method.

11. The FinFET transistor cut etching process method according to claim 1 , wherein, in step 4, the second dielectric layer is formed by means of a chemical vapor deposition process.

12. The FinFET transistor cut etching process method according to claim 1 , wherein, in step 6, the side wall is removed by means of a dry etching process.

13. The FinFET transistor cut etching process method according to claim 1 , wherein, in step 8, the first hard mask and the semiconductor substrate are sequentially etched by means of a dry etching process.

14. The FinFET transistor cut etching process method according to claim 3 , wherein, in step 7, an etching solution of the wet process comprises TMAH and NH 4 OH.

15. The FinFET transistor cut etching process method according to claim 1 , further comprising a step of forming a gate structure of the FinFET transistor after step 8, the gate structure comprising a gate dielectric layer and a gate conductive material layer and covering a side surface and a top surface of the fin; and
further comprising a step of forming a source region and a drain region in fins on two sides of the gate structure.

Assignees

• Shanghai Huali Integrated Circuit Corp

Inventors

• Chiu Yenchan
• Chen Yingju
• Liu Liyao
• Hu Chanyuan

Classifications

• H10P76/204

  of organic photoresist masks · CPC title

• H10P52/402

  of semiconductor materials · CPC title

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P50/242

  of Group IV materials · CPC title