Display substrate and display device

Patent metadata

Field	Value
Publication number	US-12588360-B2
Application number	US-202218040983-A
Country	US
Kind code	B2
Filing date	Apr 28, 2022
Priority date	Apr 28, 2022
Publication date	Mar 24, 2026
Grant date	Mar 24, 2026

Abstract

A display substrate and a display device are provided. The display substrate includes: a plurality of pixel units arranged on a base substrate; a first conductive layer, a semiconductor layer, a second conductive layer and a pixel definition layer sequentially arranged on the base substrate. A pixel driving circuit includes a sensing transistor, a storage capacitance and a capacitance wire. A source electrode and a drain electrode of the sensing transistor are located in the second conductive layer, a second capacitance electrode of the storage capacitance and the capacitance wire are located in the first conductive layer. The capacitance wire includes a capacitance wire body portion extending in a second direction. For one same sub-pixel, an orthographic projection of the capacitance wire body portion of the pixel driving circuit thereof on the base substrate is spaced apart from that of the light emitting region thereof on the base substrate.

First claim

What is claimed is:

1 . A display substrate, comprising:
a base substrate; a plurality of pixel units arranged on the base substrate, wherein the plurality of pixel units are arranged in an array in a first direction and a second direction, at least one pixel unit comprises a plurality of sub-pixels, and at least one sub-pixel comprises a light emitting element and a pixel driving circuit for driving the light emitting element; a semiconductor layer arranged on the base substrate; a first conductive layer arranged on a side of the semiconductor layer close to the base substrate; a second conductive layer arranged on a side of the semiconductor layer away from the base substrate; and a pixel definition layer arranged on a side of the second conductive layer away from the base substrate, wherein the pixel definition layer comprises a plurality of openings for defining light emitting regions of the plurality of sub-pixels, wherein the pixel driving circuit comprises a sensing transistor, a storage capacitance and a capacitance wire, the sensing transistor comprises a source electrode and a drain electrode, the storage capacitance comprises a first capacitance electrode and a second capacitance electrode arranged opposite to each other, and the capacitance wire is configured to electrically connect one of the source electrode and the drain electrode of the sensing transistor with the second capacitance electrode; wherein the source electrode and the drain electrode of the sensing transistor are located in the second conductive layer, the second capacitance electrode and the capacitance wire are located in the first conductive layer, and the capacitance wire comprises a capacitance wire body portion extending in the second direction; and wherein for one and the same sub-pixel, an orthographic projection of the capacitance wire body portion of the pixel driving circuit of the sub-pixel on the base substrate is spaced apart from an orthographic projection of the light emitting region of the sub-pixel on the base substrate; wherein the display substrate further comprises a data line for supplying a data signal, the data line is located in the second conductive layer, and the data line comprises a data line body portion extending in the second direction; and wherein for one and the same sub-pixel, the data line body portion of the data line configured to supply the data signal to the pixel driving circuit of the sub-pixel has an orthographic projection on the base substrate that at least partially overlaps with an orthographic projection of the capacitance wire body portion of the pixel driving circuit of the sub-pixel on the base substrate.

2 . The display substrate according to claim 1 , wherein for one and the same sub-pixel, the data line body portion of the data line configured to supply the data signal to the pixel driving circuit of the sub-pixel has an orthographic projection on the base substrate that completely covers the orthographic projection of the capacitance wire body portion of the pixel driving circuit of the sub-pixel on the base substrate.

3 . The display substrate according to claim 1 , wherein for one and the same sub-pixel, an orthographic projection of the second capacitance electrode of the pixel driving circuit of the sub-pixel on the base substrate at least partially overlaps with the orthographic projection of the light emitting region of the sub-pixel on the base substrate; and
wherein the capacitance wire comprises a first connecting portion and a second connecting portion, the capacitance wire body portion is located between the first connecting portion and the second connecting portion, the first connecting portion is connected to the second capacitance electrode, and the second connecting portion is electrically connected to one of the source electrode and the drain electrode of the sensing transistor.

4 . The display substrate according to claim 3 , wherein the display substrate further comprises a third conductive layer located between the semiconductor layer and the second conductive layer;
wherein the display substrate further comprises a first auxiliary wire located in the third conductive layer, the first auxiliary wire extends in the second direction, and the first auxiliary wire is electrically connected to the data line; and wherein for one and the same sub-pixel, the first auxiliary wire electrically connected to the data line configured to supply a data signal to the pixel driving circuit of the sub-pixel has an orthographic projection on the base substrate that at least partially overlaps with the orthographic projection of the capacitance wire body portion of the pixel driving circuit of the sub-pixel on the base substrate.

5 . The display substrate according to claim 3 , wherein the first capacitance electrode is located in the semiconductor layer; and
wherein for one and the same sub-pixel, an orthographic projection of the first capacitance electrode of the pixel driving circuit of the sub-pixel on the base substrate at least partially overlaps with the orthographic projection of the light emitting region of the sub-pixel on the base substrate.

6 . The display substrate according to claim 4 , wherein the display substrate further comprises a first scanning signal line and a second scanning signal line for supplying gate scanning signals, and the first scanning signal line and the second scanning signal line are located in the third conductive layer;
wherein the pixel driving circuit further comprises a switching transistor, a part of the first scanning signal line overlapping with the semiconductor layer is a gate electrode of the switching transistor, and a part of the second scanning signal line overlapping with the semiconductor layer is a gate electrode of the sensing transistor; and wherein the first scanning signal line and the second scanning signal line configured to supply gate scanning signals to the pixel driving circuits of one and the same row of sub-pixels are respectively located on two sides of the light emitting regions of the same row of sub-pixels in the second direction.

7 . The display substrate according to claim 6 , wherein the display substrate further comprises a fourth conductive layer between the first conductive layer and the semiconductor layer;
wherein the display substrate further comprises a third conductive connecting portion located in the fourth conductive layer and a third semiconductor portion located in the semiconductor layer, the third semiconductor portion comprises a third source region, a third drain region and a channel region of the sensing transistor, and the third source region and the third drain region are respectively located on two sides of the channel region of the sensing transistor; and wherein the third conductive connecting portion comprises a first part and a second part, an orthographic projection of the first part of the third conductive connecting portion on the base substrate overlaps with an orthographic projection of the second connecting portion of the capacitance wire on the base substrate, and an orthographic projection of one of the third source region and the third drain region on the base substrate overlaps with an orthographic projection of the second part of the third conductive connecting portion on the base substrate.

8 . The display substrate according to claim 7 , wherein the display substrate further comprises a first insulation layer and a second insulation layer, and the first insulation layer and the second insulation layer are located between the third conductive layer and the second conductive layer;
wherein the display substrate comprises a first via hole penetrating the first insulation layer and a second via

Assignees

• Hefei Xinsheng Optoelectronics Technology Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Zhang Yang
• Wang Qinghe
• Wang Haitao
• Wang Duoduo
• Liu Shan
• Zhang Xiaodong

Classifications

• H10K59/1315

  comprising structures specially adapted for lowering the resistance · CPC title

• H10K59/1216 Primary

  the pixel elements being capacitors · CPC title

• H10K59/124

  Insulating layers formed between TFT elements and OLED elements · CPC title

• H10K59/122

  Pixel-defining structures or layers, e.g. banks · CPC title

• H10K59/131

  Interconnections, e.g. wiring lines or terminals · CPC title