Display Substrate, Manufacturing Method Thereof, and Display Apparatus

Patent metadata

Field	Value
Publication number	US-2022013612-A1
Application number	US-202017281266-A
Country	US
Kind code	A1
Filing date	Aug 19, 2020
Priority date	Oct 29, 2019
Publication date	Jan 13, 2022
Grant date	—

Abstract

Provided are a display substrate, a manufacturing method thereof and a display apparatus. The display substrate includes multiple sub-pixels, wherein each sub-pixel includes a light-emitting region and a non-light-emitting region, and each sub-pixel is provided with a drive circuit; the drive circuit includes a storage capacitor and multiple transistors; for each sub-pixel, the multiple transistors are in the non-light-emitting region, the storage capacitor is a transparent capacitor, and an orthographic projection of the storage capacitor on a base substrate coincides with the light-emitting region. A first electrode of the storage capacitor is disposed in a same layer as an active layer of the multiple transistors, but in a different layer from source and drain electrodes of the multiple transistors, and a second electrode of the storage capacitor is on a side of the first electrode close to the base substrate.

First claim

What is claimed is:

1 . A display substrate, comprising: a base substrate and a plurality of sub-pixels disposed on the base substrate, wherein each sub-pixel comprises a light-emitting region and a non-light-emitting region, and a drive circuit is provided in each sub-pixel; the drive circuit comprises a storage capacitor and a plurality of transistors; the plurality of transistors comprise a switch transistor, a drive transistor and a sense transistor;
for each sub-pixel, the plurality of transistors are in the non-light-emitting region, the storage capacitor is a transparent capacitor, and an orthographic projection of the storage capacitor on the base substrate coincides with the light-emitting region; a first electrode of the storage capacitor is disposed in a same layer as an active layer of the plurality of transistors and in a different layer from source and drain electrodes of the plurality of transistors, and a second electrode of the storage capacitor is on a side of the first electrode close to the base substrate; and a first electrode of the drive transistor is connected to the second electrode of the storage capacitor through an active layer of the drive transistor, and a first electrode of the sense transistor is connected to the second electrode of the storage capacitor through an active layer of the sense transistor.

2 . The display substrate according to claim 1 , wherein for each sub-pixel, an active layer of each transistor comprises a channel region, a first conductive region and a second conductive region;
the first conductive region and the second conductive region are respectively disposed on two sides of the corresponding channel region, a second electrode of each of the plurality of transistors is connected to the first conductive region, and a first electrode of each of the plurality of transistors is connected to the second conductive region; and a second conductive region of the drive transistor is connected to the second electrode of the storage capacitor, and a second conductive region of the sense transistor is connected to the second electrode of the storage capacitor.

3 . The display substrate according to claim 2 , further comprising a buffer layer disposed on a side of the active layer of the plurality of transistors close to the base substrate, wherein the buffer layer comprises a first via hole and a second via hole that expose the second electrode of the storage capacitor; and
the second conductive region of the drive transistor is connected to the second electrode of the storage capacitor through the first via hole, and the second conductive region of the sense transistor is connected to the second electrode of the storage capacitor through the second via hole.

4 . The display substrate according to claim 3 , wherein the drive transistor further comprises a light shield layer disposed on a side of the buffer layer close to the base substrate;
the second electrode of the storage capacitor is disposed on the side of the buffer layer close to the base substrate, an orthographic projection of the second electrode on the base substrate covers an orthographic projection of the light shield layer on the base substrate, and a surface of the light shield layer close to the second electrode is completely in contact with the second electrode; and the light shield layer is disposed on a side of the second electrode close to the base substrate, or the second electrode is disposed on a side of the light shield layer close to the base substrate.

5 . The display substrate according to claim 3 , further comprising a plurality of rows of gate lines and a plurality of columns of data lines disposed on the base substrate; wherein each sub-pixel is defined by intersection of gate lines and data lines, and the plurality of sub-pixels respectively correspond to the plurality of rows of gate lines and the plurality of columns of data lines one by one, wherein the plurality of rows of gate lines comprise a first gate line and a second gate line,
the first gate line and the second gate line are disposed in a same layer as gate electrodes of the plurality of transistors, and the plurality of columns of data lines are disposed in a same layer as the source and drain electrodes of the plurality of transistors.

6 . The display substrate according to claim 5 , wherein for each sub-pixel, the first electrode of the storage capacitor is respectively connected to a first electrode of the switch transistor and a gate electrode of the drive transistor;
a gate electrode of the switch transistor is connected to the first gate line among the gate lines corresponding to the sub-pixel; a second electrode of the switch transistor is connected to a data line corresponding to the sub-pixel, and a gate electrode of the sense transistor is connected to the second gate line among the gate lines corresponding to the sub-pixel.

7 . The display substrate according to claim 6 , wherein, for each sub-pixel, the non-light-emitting region comprises a first non-light-emitting region and a second non-light-emitting region, the first non-light-emitting region and the second non-light-emitting region are on two sides of the light-emitting region and are disposed along an extending direction of the plurality of columns of data lines;
the sense transistor and the second gate line are both in the first non-light-emitting region, and the switch transistor, the drive transistor and the first gate line are all in the second non-light-emitting region.

8 . The display substrate according to claim 5 , further comprising power supply lines and sense lines disposed in a same layer as the plurality of columns of data lines, wherein each pixel comprises four sub-pixels disposed along an extending direction of the plurality of rows of gate lines, each pixel corresponding to two columns of power supply lines and one column of sense line;
for each pixel, the sense line corresponding to the pixel is between a second sub-pixel and a third sub-pixel, one column of power supply line corresponding to the pixel is on a side of a first sub-pixel away from the second sub-pixel, and another column of power supply line corresponding to the pixel is on a side of a fourth sub-pixel away from the third sub-pixel; a data line corresponding to the first sub-pixel is on a side of the first sub-pixel close to the second sub-pixel; a data line corresponding to the second sub-pixel is on a side of the second sub-pixel close to the first sub-pixel; a data line corresponding to the third sub-pixel is on a side of the third sub-pixel close to the fourth sub-pixel, and a data line corresponding to the fourth sub-pixel is on a side of the fourth sub-pixel close to the third sub-pixel; the display substrate further comprises power supply connection lines disposed in the same layer as the gate electrodes of the plurality of transistors and sensing connection lines disposed in a same layer as a light shield layer, each pixel corresponds to two power supply connection lines disposed along the extending direction of the gate lines and two sensing connection lines disposed along the extending direction of the gate lines; the power supply connection lines respectively correspond to power supply lines; the power supply connection lines are connected to the corresponding power supply lines; the two sensing connection lines are connected to the sense lines; a second electrode of a drive transistor of the second sub-pixel is connected to one of the power supply connection lines; a second electrode of a drive transistor of the third sub-pixel is connected to another one of the power supply connection lines; a second electrode of a sense transistor of the first sub-pixel is connected to one of the sensing c

Assignees

• Boe Technology Group Co Ltd

Inventors

• Xu Pan
• Li Yongqian
• Wang Guoying
• Zhang Dacheng
• Xu Chen
• Liu Lang
• Zhang Xing
• Wang Ling
• Lin Yicheng
• Han Ying

Classifications

• H10D84/01

  Manufacture or treatment · CPC title

• H01L27/3262

  Electricity · mapped topic

• H01L27/3272

  Electricity · mapped topic

• H01L2227/323

  Electricity · mapped topic

• H01L27/3265 Primary

  Electricity · mapped topic