Ramp signal generator and image sensor and electronic device including the same

Patent metadata

Field	Value
Publication number	US-12587767-B2
Application number	US-202418900069-A
Country	US
Kind code	B2
Filing date	Sep 27, 2024
Priority date	Oct 5, 2023
Publication date	Mar 24, 2026
Grant date	Mar 24, 2026

Abstract

A ramp signal generator includes a resistor connected between an output node outputting a ramp signal that increases or decreases at a constant slope and a first power node which receives a first power voltage, and plural current cells. A cell current flows through each of the current cells to the first power node or the resistor. The current cells include a first current cell. The first current cell includes a first transistor connected between a first switching node and the output node, the cell current flowing to the resistor through the first transistor, a second transistor connected between the first switching node and the first power node, the cell current flowing to the first power node through the second transistor, and a negative feedback circuit that maintains a constant voltage at the first switching node.

First claim

What is claimed is:

1 . A ramp signal generator comprising:
a resistor connected between an output node outputting a ramp signal that increases or decreases at a constant slope and a first power node which is configured to receive a first power voltage; and a plurality of current cells, a cell current flowing through each of the plurality of current cells to the first power node or the resistor, the plurality of current cells including at least one first current cell, wherein the at least one first current cell comprises:
a first transistor connected between a first switching node and the output node, the cell current flowing to the resistor through the first transistor;
a second transistor connected between the first switching node and the first power node, the cell current flowing to the first power node through the second transistor; and
a negative feedback circuit that maintains a constant voltage at the first switching node by controlling a gate terminal of the first transistor based on a voltage of the first switching node.

2 . The ramp signal generator of claim 1 , wherein the negative feedback circuit comprises:
a load transistor including a first terminal connected to a second power node which is configured to receive a second power voltage, a second terminal connected to a bias node, and a gate terminal connected to the first switching node; a current source connected between the bias node and the first power node; a first switch connected to the bias node and the gate terminal of the first transistor, the first switch being turned on or off based on a first control signal; and a second switch connected to the bias node and a gate terminal of the second transistor, the second switch being turned on or off based on a second control signal that is a complementary signal of the first control signal.

3 . The ramp signal generator of claim 2 , wherein the at least one first current cell further comprises:
a bias transistor connected between the second power node and the first switching node, the bias transistor generating the cell current; a third switch connected between the second power node and the gate terminal of the first transistor, the third switch being turned on based on the first control signal to turn off the first transistor; and a fourth switch connected between the second power node and the gate terminal of the second transistor, the fourth switch being turned on based on the second control signal to turn off the second transistor.

4 . The ramp signal generator of claim 3 , wherein, in a reset phase, the second transistor is turned off, and the first transistor is turned on to provide the cell current to the resistor.

5 . The ramp signal generator of claim 4 , wherein the first transistor operates in a saturation region.

6 . The ramp signal generator of claim 4 , wherein, in a set phase after the reset phase, the first transistor is turned off, and the second transistor is turned on to provide the cell current to the first power node.

7 . The ramp signal generator of claim 6 , wherein:
in the reset phase, the first switch and the fourth switch are turned on, and the second switch and the third switch are turned off, and in the set phase, the first switch and the fourth switch are turned off, and the second switch and the third switch are turned on.

8 . The ramp signal generator of claim 2 , wherein:
the first power voltage is less than the second power voltage, and each of the first transistor and the second transistor includes a P-type transistor.

9 . The ramp signal generator of claim 1 , wherein:
the plurality of current cells are sequentially changed from a reset phase to a set phase, and the first transistor provided in the at least one first current cell in the reset phase among the plurality of current cells operate in a saturation region and provide the cell current to the resistor.

10 . The ramp signal generator of claim 1 , wherein each of the plurality of current cells includes the first current cell.

11 . The ramp signal generator of claim 1 , wherein the plurality of current cells include the at least one first current cell and at least one second current cell, wherein the at least one second current cell comprises:
a bias transistor connected between a second power node which is configured to receive a second power voltage and a second switching node, the bias transistor generating the cell current; a third transistor connected between the second switching node and a first terminal of the resistor, the cell current flowing to the resistor through the third transistor; and a fourth transistor connected between the second switching node and the first power node, the cell current flowing to the first power node through the fourth transistor.

12 . The ramp signal generator of claim 11 , wherein:
a level of the ramp signal decreases as the plurality of current cells are sequentially changed from a reset phase to a set phase; in the reset phase, the first transistor and the third transistor are turned on, and the second transistor and the fourth transistor are turned off; in the set phase, the second transistor and the fourth transistor are turned on, and the first transistor and the third transistor are turned off; and the at least one second current cell is changed to the set phase earlier than the at least one first current cell.

13 . An image sensor comprising:
a pixel array including a plurality of pixels; a ramp signal generation circuit configured to generate a ramp signal of which a level decreases at a constant slope; and an analog-to-digital conversion circuit configured to convert a pixel signal provided from the pixel array into a pixel value based on the ramp signal, wherein the ramp signal generation circuit includes:
a load resistor connected between a ground and an output node to which the ramp signal is output, and
a plurality of current cells, each providing a cell current to the load resistor during a reset period and providing the cell current to the ground during a set period, and
wherein each of the plurality of current cells includes:
a first transistor connected between a switching node and the output node, the cell current flowing to the load resistor through the first transistor,
a second transistor connected between the switching node and the ground, the cell current flowing to the ground through the second transistor, and
a negative feedback circuit that controls a gate terminal of the first transistor based on a voltage of the switching node so that the first transistor operates in a saturation region.

14 . The image sensor of claim 13 , wherein the negative feedback circuit comprises:
a third transistor including a first terminal which is configured to receive a positive power voltage, a second terminal connected to a bias node, and a gate terminal connected to the switching node; a current source connected between the bias node and the ground; a fourth transistor connected to the bias node and the gate terminal of the first transistor, the fourth transistor being turned on or off based on a first control signal; and a fifth transistor connected to the bias node and a gate terminal of the second transistor, the fifth transistor being turned on or off based on a second control signal that is a complementary signal of the first control signal.

15 . The image sensor of claim 13 , wherein the negative feedback circuit is further configured to control the gate terminal of the first transistor based on the voltage of the switching node to keep the voltage of the switching nod

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yoon Younghyun

Classifications

• H03K4/90

  Linearisation of ramp (modifying slopes of pulses H03K6/04; scanning distortion correction for television receivers H04N3/23); Synchronisation of pulses · CPC title

• H03M1/56

  Input signal compared with linear ramp · CPC title

• H04N25/772

  comprising A/D, V/T, V/F, I/T or I/F converters · CPC title

• H04N25/7795

  Circuitry for generating timing or clock signals · CPC title

• H04N25/745

  Circuitry for generating timing or clock signals · CPC title