Ramp signal generator and CMOS image sensor using the same

Patent metadata

Field	Value
Publication number	US-11032505-B2
Application number	US-201816219826-A
Country	US
Kind code	B2
Filing date	Dec 13, 2018
Priority date	Apr 24, 2018
Publication date	Jun 8, 2021
Grant date	Jun 8, 2021

Abstract

Provided are devices having a device including a ramp signal generator which may comprise: a slope control circuit configured to generate a controllable analog reference voltage according to a digital setting code value to control a slope of a ramp signal; and at least one unit current cell configured to adjust the slope of the ramp signal by adjusting a current flowing through the at least one unit current cell according to the controllable analog reference voltage generated by the slope control circuit.

First claim

What is claimed is:

1. A device including a ramp signal generator which comprises:
a slope control circuit configured to generate a controllable analog reference voltage according to a digital setting code value to control a slope of a ramp signal; and
at least one unit current cell configured to adjust the slope of the ramp signal by adjusting a current flowing through the at least one unit current cell according to the controllable analog reference voltage generated by the slope control circuit,
wherein the slope control circuit comprises:
a code providing circuit configured to provide the digital setting code value,
wherein the code providing circuit comprises:
a memory configured to receive the digital setting code value from an external image signal processor (ISP), store the digital setting code value, and provide the digital setting code value to the controllable reference voltage generation circuit.

2. The device of claim 1 , wherein the slope control circuit further comprises:
a controllable reference voltage generation circuit configured to generate the controllable analog reference voltage according to the digital setting code value provided by the code providing circuit.

3. The device of claim 2 , wherein the code providing circuit further comprises:
a buffer configured to apply to the at least one unit current cell the controllable analog reference voltage generated by the controllable reference voltage generation circuit.

4. The device of claim 3 , wherein the buffer includes a source follower circuit.

5. The device of claim 2 , wherein the controllable reference voltage generation circuit includes a digital-to-analog converter (DAC).

6. The device of claim 1 , wherein a level of an ON/OFF voltage of the at least one unit current cell is adjusted according to the controllable analog reference voltage generated by the slope control circuit.

7. The device of claim 1 , wherein the ramp signal generator adjusts the slope of the ramp signal by adjusting a current flowing through the at least one unit current cell.

8. A device including a CMOS image sensor which comprises:
a pixel array configured to include an array of photosensing pixels in rows and columns to output a pixel signal corresponding to incident light;
a row decoder configured to select and control pixels in the pixel array according to row lines coupled to rows of photosensing pixels;
a ramp signal generator configured to adjust a slope of a ramp signal by adjusting a channel current flowing through an analog switch device based on an analog voltage that is adjustable in response to a digital code;
a comparison circuit configured to compare the ramp signal applied from the ramp signal generator with each pixel signal of the pixel array;
a counting circuit configured to count a number of clock pulses according to each output signal of the comparison circuit;
a memory circuit configured to store counting information of the counting circuit including the number of clock pulses provided by the counting unit;
a control circuit configured to control operations of the row decoder, the ramp signal generator, the comparison circuit, the counting circuit, and the memory circuit; and
a column readout circuit configured to output data stored in the memory circuit according to instructions provided by the control circuit,
wherein the ramp signal generator comprises:
a slope control circuit configured to generate a controllable analog reference voltage according to a digital setting code value to adjust the slope of the ramp signal,
wherein the slope control circuit comprises:
a code providing circuit configured to provide the digital setting code value,
wherein the code providing circuit comprises:
a memory configured to receive the digital setting code value from an external image signal processor (ISP), store the digital setting code value, and provide the digital setting code value to the controllable reference voltage generation circuit.

9. The device of claim 8 , wherein the ramp signal generator further comprises:
at least one unit current cell configured to adjust the slope of the ramp signal according to the controllable analog reference voltage generated by the slope control circuit.

10. The device of claim 9 , wherein the slope control circuit further comprises:
a controllable reference voltage generation circuit configured to generate the controllable analog reference voltage according to the digital setting code value provided by the code providing circuit.

11. The device of claim 10 , wherein the code providing circuit further comprises:
a buffer configured to apply to the at least one unit current cell the controllable reference voltage of the controllable reference voltage generation circuit.

12. The device of claim 11 , wherein the buffer include a source follower circuit.

13. The device of claim 10 , wherein the controllable reference voltage generation circuit includes a digital-to-analog converter (DAC).

14. The device of claim 9 , wherein a level of an ON/OFF voltage of the at least one unit current cell is adjusted according to the controllable analog reference voltage generated by the slope control circuit.

15. The device of claim 9 , wherein the ramp signal generator adjusts the slope of the ramp signal by adjusting a current flowing through the at least one unit current cell.

16. A device including a ramp signal generator which comprises:
a unit current cell including a current path that allows an electrical current constituting a ramp signal to flow from a ramp supply voltage terminal to a ramp resistor, the current path including an analog switch device coupled between the ramp supply voltage terminal and the ramp resistor; and
a slope control circuit coupled to the analog switch device and configured to receive a digital setting code value and generate a controllable analog reference voltage in response to the digital setting code value to apply the controllable analog reference voltage to the analog switch device to control a slope of a ramp signal,
wherein the unit current cell adjusts the slope of the ramp signal by adjusting a channel current flowing through the analog switch device based on the controllable analog reference voltage, which is adjustable in response to the digital setting code value,
wherein the slope control circuit comprises:
a code providing circuit configured to provide the digital setting code value,
wherein the code providing circuit comprises:
a memory configured to receive the digital setting code value from an external image signal processor (ISP), store the digital setting code value, and provide the digital setting code value to the controllable reference voltage generation circuit.

17. The device of claim 16 , wherein the slope control circuit further includes a digital-to-analog converter (DAC) that converts the digital setting code value to the controllable analog reference voltage.

Assignees

• Sk Hynix Inc

Inventors

• Kim Hyeon-June
• Jeong Hoe-Sam

Classifications

• H10F39/182 Primary

  Colour image sensors · CPC title

• H04N25/77

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

• H04N25/78 Primary

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• H04N25/7795

  Circuitry for generating timing or clock signals · CPC title

• H04N25/76 Primary

  Addressed sensors, e.g. MOS or CMOS sensors · CPC title