SRAM with tracking circuitry for reducing active power

Patent metadata

Field	Value
Publication number	US-11727972-B2
Application number	US-202117459624-A
Country	US
Kind code	B2
Filing date	Aug 27, 2021
Priority date	Aug 27, 2021
Publication date	Aug 15, 2023
Grant date	Aug 15, 2023

Abstract

A memory device is disclosed. The memory device includes word lines, a tracking bit line and a word line driver. The word lines are configured to transmit word line signals to memory cells. The tracking bit line is coupled to a first plurality of tracking cells that are arranged in rows. The word line driver is coupled to the word lines and a control circuit that is coupled through the tracking bit line to the word lines. The word line driver is configured to control a falling edge of each of the word line signals, by receiving each corresponding tracking bit line signal of tracking bit line signals transmitted from the tracking bit line, based on a resistance of a length of the tracking bit line. The length is substantially distanced from each corresponding row of the rows to the control circuit. A method is also disclosed herein.

First claim

What is claimed is:

1. A memory device, comprising:
a plurality of word lines configured to transmit word line signals to memory cells;
a tracking bit line coupled to a first plurality of tracking cells that are arranged in rows;
a word line driver coupled to the plurality of word lines and a control circuit that is coupled through the tracking bit line to the plurality of word lines, wherein the word line driver is configured to control a falling edge of each of the word line signals, by receiving each corresponding tracking bit line signal of tracking bit line signals transmitted from the tracking bit line, based on a resistance of a length of the tracking bit line, wherein the length is substantially distanced from each corresponding row of the rows to the control circuit; and
a second plurality of tracking cells respectively coupled to the plurality of word lines,
wherein each of the second plurality of tracking cells is configured to pull low a voltage level of the tracking bit line for generating a falling edge of each of the tracking bit line signals.

2. The memory device of claim 1 ,
wherein the second plurality of tracking cells is further coupled to the tracking bit line,
wherein each of the second plurality of tracking cells is configured to pull low the voltage level of the tracking bit line for generating the falling edge of each of the tracking bit line signals, in response to a rising edge of each corresponding word line signal of the word line signals.

3. The memory device of claim 2 , wherein
each of the second plurality of tracking cells comprises a latch circuit and a pair of transistors,
wherein the latch circuit is coupled between the pair of transistors,
gate terminals of the pair of transistors are coupled to one of the plurality of word lines, and
a first terminal of one of the pair of transistors is coupled to the tracking bit line.

4. The memory device of claim 1 , further comprising:
a plurality of pull-down transistors,
wherein gate terminals of the plurality of pull-down transistors are respectively coupled to the plurality of word lines;
first terminals of the plurality of pull-down transistors are coupled together to the tracking bit line; and
second terminals of the plurality of pull-down transistors are coupled to a reference node.

5. The memory device of claim 1 , wherein the word line driver comprises:
a plurality of decoded address lines coupled to the plurality of word lines, and configured to transmit decoded address line signals, for selecting one of the plurality of word lines to transmit a selected word line signal of the word line signals; and
a second plurality of tracking cells respectively coupled between the tracking bit line and the plurality of decoded address lines,
wherein each of the second plurality of tracking cells is configured to pull down the voltage level of the tracking bit line to a reference voltage level, for generating a falling edge of one of the tracking bit line signals, in response to one of the decoded address line signals.

6. The memory device of claim 5 , wherein
the tracking bit line is coupled to the control circuit at a common node,
the second plurality of tracking cells comprising a transistor,
a gate terminal of the transistor is coupled to one of the plurality of decoded address lines, and a first terminal of the transistor is coupled to the tracking bit line at a tracking node,
a first tracking bit line signal of the tracking bit line signals having the pulled down voltage level is transmitted through the tracking bit line, within a tracking length from the tracking node to the common node, to the control circuit, wherein the tracking bit line transmitted with the first tracking bit line signal has a resistance that is associated with the tracking length, and
the word line driver is configured to generate a falling edge of the selected word line signal, in response to the one of the tracking bit line signals.

7. The memory device of claim 1 , further comprising:
a plurality of tracking word lines coupled to the first plurality of tracking cells, and comprising a selected tracking word line,
wherein the selected tracking word line is coupled to a selected first tracking cell of the first plurality of tracking cells that is arranged at a selected row of the rows and is coupled to the tracking bit line at a node,
the selected tracking word line is configured to transmit a tracking word line signal to the selected first tracking cell, when one of the word line signals is transmitted through one of the plurality of word lines, and
in response to a rising edge of the tracking word line signal, the selected first tracking cell is configured to pull low the voltage level of the tracking bit line at the node.

8. A memory device, comprising:
a word line driver configured to select a first word line of word lines, for transmitting a first word line signal through the first word line to memory cells arranged at a first row;
a tracking circuit coupled to the word line driver, and comprising a tracking bit line and a first plurality of tracking cells, wherein the tracking circuit is configured to generate a first tracking bit line signal, based on a first resistance of a first length of the tracking bit line, wherein the first length is distanced from a first tracking node to a common node; and
a control circuit coupled to the word line driver and the tracking circuit, and configured to control a pulse width of the first word line signal by triggering a falling edge of the first word line signal, in response to the first tracking bit line signal,
wherein the first tracking node is coupled with the tracking bit line and a first tracking cell of the first plurality of tracking cells, and the common node is coupled with the tracking bit line and the control circuit,
the word line driver comprises a first decoded address line, and the first decoded address line is coupled to the word lines of a first group that comprises the first word line,
the first tracking cell comprises a first transistor, and
a gate terminal of the first transistor is coupled to the first decoded address line, and a first terminal of the first transistor is coupled to the tracking bit line at the first tracking node.

9. The memory device of claim 8 , wherein
the first tracking cell is arranged at the first row,
a second tracking cell of the first plurality of tracking cells is arranged at a second row, and is coupled to a second word line of the word lines and coupled to the tracking bit line at a second tracking node,
when the second word line is selected by the word line driver, the second tracking cell pulls low a voltage level of the second tracking node, and a second tracking bit line signal is transmitted through the tracking bit line to the control circuit,
the second tracking bit line signal is associated with a second resistance of a second length of the tracking bit line, wherein the second length is distanced from the second tracking node to the common node, and
the second length is different from the first length, and the second resistance is different from the first resistance.

10. The memory device of claim 8 , wherein
the first tracking cell comprises a latch circuit, a second transistor, and a third transistor,
the latch circuit is coupled between the second transistor and the third transistor, and is coupled to between a first reference node and a second reference node,
gate terminals of the second transistor and the third transistor are coupled to the first word line, and
the second transistor and the third transistor are configured to turn on the latch circuit, in response to a rising edge of the first word l

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Tsung-Hsien
• Hsieh Wei-Jer
• Hsu Yu-Hao

Classifications

• G11C8/18 Primary

  Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals · CPC title

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C11/412

  using field-effect transistors only · CPC title

• G11C11/413

  Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction · CPC title

• G11C11/419

  Read-write [R-W] circuits · CPC title