Methods for fusion bonding semiconductor devices to temporary carrier wafers with cavity regions for reduced bond strength, and semiconductor device assemblies formed by the same

Patent metadata

Field	Value
Publication number	US-12582001-B2
Application number	US-202217892038-A
Country	US
Kind code	B2
Filing date	Aug 19, 2022
Priority date	Aug 19, 2022
Publication date	Mar 17, 2026
Grant date	Mar 17, 2026

Abstract

Methods of making a semiconductor device assembly are provided. The methods can comprise providing a first semiconductor device having a first dielectric material at a first surface, providing a carrier wafer having a second dielectric material at a second surface, and forming a dielectric-dielectric bond between the first dielectric material and the second dielectric material. At least one of the first surface and the second surface includes a cavity configured to entrap a gas during the formation of the bond. The method can further include stacking one or more second semiconductor devices over the first semiconductor device to form the semiconductor device assembly, and removing the semiconductor device assembly from the carrier wafer.

First claim

What is claimed is:

1 . A method of making a semiconductor device assembly, the method comprising:
providing a first semiconductor device having a first dielectric material at a first surface; providing a carrier wafer having a second dielectric material at a second surface; forming a dielectric-dielectric bond between the first dielectric material and the second dielectric material, wherein the first surface includes a cavity configured to entrap a gas during the formation of the dielectric-dielectric bond; stacking one or more second semiconductor devices over the first semiconductor device to form the semiconductor device assembly; and removing the semiconductor device assembly from the carrier wafer.

2 . The method of claim 1 , wherein the first surface is an active surface of the first semiconductor device that further includes metal interconnects.

3 . The method of claim 1 , wherein the second surface includes a second cavity configured to entrap the gas during the formation of the dielectric-dielectric bond.

4 . The method of claim 1 , wherein the cavity has an area equal to at least 25% of a footprint of the first semiconductor device.

5 . The method of claim 1 , wherein the first surface further includes a second cavity.

6 . A method of making a semiconductor device assembly, the method comprising:
providing a first semiconductor device having a first dielectric material at a first surface; providing a carrier wafer having a second dielectric material at a second surface; forming a dielectric-dielectric bond between the first dielectric material and the second dielectric material, wherein at least one of the first surface and the second surface includes a cavity configured to entrap a gas during the formation of the dielectric-dielectric bond; stacking one or more second semiconductor devices over the first semiconductor device to form the semiconductor device assembly; and removing the semiconductor device assembly from the carrier wafer, wherein removing the semiconductor device assembly from the carrier wafer includes increasing a pressure of the entrapped gas in the cavity.

7 . The method of claim 6 , wherein increasing the pressure of the entrapped gas in the cavity includes heating the entrapped gas in the cavity.

8 . The method of claim 7 , wherein heating the entrapped gas in the cavity includes providing power to a heater adjacent the cavity.

9 . The method of claim 8 , wherein the heater is formed in the first semiconductor device.

10 . The method of claim 8 , wherein the heater is formed in the carrier wafer.

11 . The method of claim 6 , wherein:
the second surface includes the cavity, a channel is formed through the carrier wafer, and the method further comprising introducing the gas into the cavity.

12 . The method of claim 11 , wherein increasing the pressure of the entrapped gas comprises introducing the gas into the cavity such that the pressure of the entrapped gas is greater than a pressure of gasses surrounding the first semiconductor device.

13 . The method of claim 12 , wherein increasing the pressure of the entrapped gas further comprises heating the entrapped gas in the cavity concurrently with introducing the gas into the cavity.

14 . The method of claim 6 , wherein respective dielectric materials at respective surfaces of the one or more second semiconductor devices exclude cavities configured to entrap gas.

15 . The method of claim 6 , wherein:
the second surface includes the cavity, and the first surface includes a mechanically-altered region corresponding to a location of the cavity on the second surface.

16 . A method of processing a semiconductor device, the method comprising:
providing the semiconductor device having a first dielectric material at a first surface; providing a carrier wafer having a second dielectric material at a second surface; forming a dielectric-dielectric bond between the first dielectric material and the second dielectric material, wherein the first surface includes a cavity configured to entrap a gas during the formation of the dielectric-dielectric bond; performing wafer-level processing on the semiconductor device while the semiconductor device is bonded to the carrier wafer; and removing the semiconductor device from the carrier wafer.

17 . The method of claim 16 , wherein removing the semiconductor device from the carrier wafer includes heating the entrapped gas in the cavity.

18 . The method of claim 17 , wherein heating the entrapped gas in the cavity includes providing power to a heater adjacent the cavity.

19 . The method of claim 18 , wherein the heater is formed in the semiconductor device.

20 . The method of claim 18 , wherein the heater is formed in the carrier wafer.

Assignees

• Micron Technology Inc

Inventors

• Zhou Wei
• Street Bret K
• Mcdaniel Terrence B
• Griffin Amy R
• Kirby Kyle K
• Raman Thiagarajan

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10P72/7434

  used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate · CPC title

• H10P72/744

  Details of chemical or physical process used for separating the auxiliary support from a device or a wafer · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title