Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-12581970-B2
Application number	US-202217941813-A
Country	US
Kind code	B2
Filing date	Sep 9, 2022
Priority date	Jun 3, 2016
Publication date	Mar 17, 2026
Grant date	Mar 17, 2026

Abstract

An electronic device and a method of manufacturing an electronic device. As non-limiting examples, various aspects of this disclosure provide various methods of manufacturing electronic devices, and electronic devices manufactured thereby, that comprise utilizing metal studs to further set a semiconductor die into the encapsulant.

First claim

What is claimed is:

1 . A method of manufacturing a semiconductor device comprising:
providing a semiconductor die having an active side, an inactive side opposite the active side, and lateral sides between the active and inactive sides, wherein the active side comprises a passivation layer on a semiconductor material, and a first bond pad exposed from the passivation layer, wherein the passivation layer covers a portion of a distal pad side of the first bond pad; forming a first metal post on the distal pad side of the first bond pad exposed from the passivation layer, the first metal post having a proximal post side, a distal post side, and a lateral post side between the proximal and distal post sides; forming a dielectric layer (DL) surrounding the first metal post, the DL having an uppermost DL side coupled to the active side, a lowermost DL side, and a lateral DL side between the uppermost DL side and the lowermost DL side, wherein the DL surrounds the first metal post, and wherein the uppermost DL side contacts the distal pad side directly laterally between the passivation layer and the lateral post side of the first metal post; encapsulating the semiconductor die with encapsulating material, the encapsulating material contacting and surrounding lateral sides of the semiconductor die and the lateral DL side, the encapsulating material comprising a first encapsulant side, a second encapsulant side, and lateral encapsulant sides between the first and second encapsulant sides; and providing a fan-out redistribution (RD) structure over the encapsulating material, the distal post side of the first metal post, and the lowermost DL side of the DL.

2 . The method of claim 1 , wherein the fan-out RD structure comprises:
an RD dielectric layer having a first side and a second side opposite the first side, the first side contacting the first encapsulant side and to the lowermost DL side; and an RD conductor structure comprising:
an RD conductive via portion that extends vertically and entirely through the RD dielectric layer without contacting the first encapsulant side and comprises a via surface that is connected to the distal post side; and
an RD conductor portion on the second side of the top RD dielectric layer, wherein the RD conductor portion extends from the RD conductive via portion and laterally away from the first metal post to a position outside a footprint of the semiconductor die.

3 . The method of claim 1 , wherein a thickness of the DL is greater than a thickness of the passivation layer.

4 . The method of claim 1 , wherein the encapsulating material extends directly vertically above and contacts the inactive side of the semiconductor die.

5 . The method of claim 1 , wherein the encapsulating material further comprises interior encapsulant sides that continuously extend from the inactive side of the semiconductor die to the fan-out RD structure and contacts the lateral sides of the semiconductor die, lateral sides of the passivation layer, and the lateral DL side, wherein the interior encapsulant sides are planar, and wherein no portion of the fan-out RD structure is laterally surrounded by the encapsulating material.

6 . The method of claim 1 , wherein the passivation layer comprises an organic dielectric material.

7 . The method of claim 6 , wherein the DL comprises an inorganic dielectric material.

8 . The method of claim 7 , wherein the organic dielectric material of the passivation layer comprises polyimide, and the inorganic dielectric material of the DL comprises at least one of Si3N4, SiO2, SiON, or SiN.

9 . The method of claim 1 , comprising forming an interconnection structure attached to the fan-out RD structure.

10 . A method of manufacturing a semiconductor device comprising:
providing a semiconductor die comprising:
a semiconductor material having an active side, an inactive side, and lateral sides between the active and inactive sides, wherein the active side comprises a first bond pad;
a passivation layer formed over the active side and extending over a distal pad side of the first bond pad, the passivation layer comprising an aperture exposing a portion of the distal pad side of the first bond pad;
a dielectric layer (DL) having an uppermost DL side oriented toward the active side, a lowermost DL side, and lateral DL sides between the uppermost and lowermost DL sides; and
a first metal post coupled to the distal pad side of the first bond pad, the first metal post having a proximal post side, a distal post side, and a lateral post side between the proximal and distal post sides, the dielectric layer surrounding the metal post, and wherein the uppermost DL side contacts the distal pad side directly laterally between the passivation layer and the lateral post side of the first metal post;
encapsulating the semiconductor die in an encapsulating material, the encapsulating material surrounding the lateral sides of the semiconductor material and the lateral DL sides, the encapsulating material comprising a first encapsulant side, a second encapsulant side, and lateral encapsulant sides between the first and second encapsulant sides; and providing a fan-out redistribution (RD) structure over the semiconductor die and the first encapsulant side.

11 . The method of claim 10 , wherein the forming the fan-out RD structure comprises:
providing an RD dielectric layer having a first side and a second side opposite the first side, the first side contacting the first encapsulant side and to the lowermost DL side; and providing an RD conductor structure comprising:
an RD conductive via portion that extends vertically and entirely through the RD dielectric layer without directly contacting the first encapsulant side and comprises a via surface that is connected to the distal post side; and
an RD conductor portion on the second side of the top RD dielectric layer, wherein the RD conductor portion extends from the RD conductive via portion and laterally away from the first metal post to a position outside a footprint of the semiconductor die.

12 . The method of claim 10 , wherein the DL comprises an inorganic dielectric material.

13 . The method of claim 10 , wherein the DL comprises at least one of an oxide or a nitride.

14 . The method of claim 10 , wherein the DL comprises at least one of Si3N4, SiO2, SiON, or SiN.

15 . The method of claim 10 , wherein a thickness of the DL is greater than a thickness of the passivation layer.

16 . The method of claim 15 , wherein the encapsulating material extends directly vertically above and contacts the inactive side of the semiconductor die.

17 . The method of claim 16 , wherein the encapsulating material comprises interior encapsulant sides that continuously extend from the inactive side of the semiconductor material to the fan-out RD structure and contacts the lateral sides of the semiconductor material, lateral sides of the passivation layer, and the lateral DL sides, wherein the interior encapsulant sides are planar, and wherein no portion of the fan-out RD structure is laterally surrounded by the encapsulating material.

18 . A semiconductor device: comprising:
a semiconductor die having an active side, an inactive side, lateral sides between the active and inactive sides, and a first bond pad on the active side; a passivation layer formed over the active side and extending over a distal pad side of the first bond pad, the passivation layer comprising an aperture exposing a portion of the first bond pad; a dielectric layer (DL) having an uppermo

Assignees

• Amkor Tech Singapore Holding Pte Ltd

Inventors

• Baloglu Bora
• Huemoeller Ron
• Zwenger Curtis

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W74/10 Primary

  characterised by their shape or disposition · CPC title

• H10W72/9413

  on encapsulations · CPC title