Semiconductor package having heat dissipating member

Patent metadata

Field	Value
Publication number	US-9269647-B2
Application number	US-201514723834-A
Country	US
Kind code	B2
Filing date	May 28, 2015
Priority date	May 29, 2014
Publication date	Feb 23, 2016
Grant date	Feb 23, 2016

Abstract

A semiconductor package includes a substrate having an upper surface and a lower surface, a semiconductor chip which is mounted on the upper surface of the substrate, and in an upper surface of which a first recess portion is provided, a molding member formed such that the molding member exposes the upper surface of the semiconductor chip and covers the semiconductor chip on the upper surface of the substrate, and a first heat dissipating member formed in the first recess portion, wherein the first heat dissipating member includes moisture absorption particles and a heat dissipation molding member.

First claim

What is claimed is:

1. A semiconductor package comprising:
a substrate having an upper surface and a lower surface;
a semiconductor chip mounted on the upper surface of the substrate, the semiconductor chip including an upper surface, and the upper surface including a first recess portion;
a molding member that exposes the upper surface of the semiconductor chip and is disposed between the semiconductor chip and the upper surface of the substrate; and
a first heat dissipating member formed in the first recess portion, wherein the first heat dissipating member comprises at least one moisture absorption particle and a heat dissipation molding member.

2. The semiconductor package of claim 1 , wherein the upper surface of the semiconductor chip comprises a protrusion portion defined by the first recess portion, and the protrusion portion has a matrix structure.

3. The semiconductor package of claim 1 , wherein the first recess portion has a depth that is equal to or less than 100 μm.

4. The semiconductor package of claim 1 , further comprising:
a second recess portion provided on an upper surface of the molding member; and
a second heat dissipating member formed in the second recess portion.

5. The semiconductor package of claim 1 , wherein the moisture absorption particle absorbs moisture around the semiconductor package at room temperature.

6. The semiconductor package of claim 1 , wherein the moisture absorption particles is formed from at least one of sodium polyacrylate, polyacrylic alcohol-based copolymer, polyacryl amide, potassium polyacrylate, polyacrylic acid, silica gel, molecular sieve, montmorillonite clay, and zeolite.

7. The semiconductor package of claim 1 , wherein the heat dissipating molding member is formed from an epoxy-group molding resin or a polyimide-group molding resin.

8. The semiconductor package of claim 1 , further comprising:
a bump interposed between the semiconductor chip and the substrate; and
the semiconductor chip is mounted on the substrate by using the bump as a medium.

9. The semiconductor package of claim 8 , further comprising an under-fill covering the bump between the semiconductor chip and the substrate.

10. The semiconductor package of claim 1 , wherein the substrate has an opening slit formed in a central portion thereof, and the semiconductor chip is mounted on the substrate in a face-down manner.

11. The semiconductor package of claim 1 , wherein an upper surface of the heat dissipating member is lower than the upper surface of the semiconductor chip.

12. The semiconductor package of claim 1 , wherein an upper surface of the heat dissipating member is located at the same height as the upper surface of the semiconductor chip.

13. The semiconductor package of claim 1 , wherein an upper surface of the heat dissipating member is higher than the upper surface of the semiconductor chip.

14. A semiconductor package comprising:
a substrate having an upper surface and a lower surface;
a semiconductor chip mounted on the upper surface of the substrate;
a molding member which is formed such that the molding member covers an upper surface and a side surface of the semiconductor chip on the upper surface of the substrate, and in an upper surface of which a recess portion is formed; and
a heat dissipating member formed in the recess portion, wherein the heat dissipating member comprises a plurality of moisture absorption particles and a heat dissipation molding member.

15. The semiconductor package of claim 14 , wherein a lower surface of the recess portion is higher than the upper surface of the semiconductor chip.

16. A semiconductor package comprising:
a substrate;
at least one semiconductor device, the at least one semiconductor device mounted on the upper surface of the substrate;
a molding member, the molding member including at least one heat dissipating member, formed such that the molding member covers an upper surface and a side surface of the semiconductor chip on the upper surface of the substrate, and in an upper surface of which a recess portion is formed, the at least one heat dissipating member formed in the recess portion and
the heat dissipating member including a plurality of moisture absorption particles and a heat dissipation molding member; and wherein the at least one semiconductor device includes a plurality of semiconductor devices arranged in a stacked manner.

17. The semiconductor package of claim 16 , wherein the semiconductor device includes at least one heat dissipating member disposed on an upper surface of the semiconductor device.

18. The semiconductor package of claim 16 , wherein
the molding member covers the exposed surfaces of the plurality of semiconductor devices.

19. The semiconductor package of claim 16 , wherein the moisture absorption particles are formed from a moisture absorption substance.

20. The semiconductor package of claim 16 , wherein the molding member defines the exposed surface of the semiconductor device.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Du Maohua

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title