Method and apparatus of deskew process for a circuitry, computer storage medium, and terminals

Patent metadata

Field	Value
Publication number	US-12580723-B2
Application number	US-202418661488-A
Country	US
Kind code	B2
Filing date	May 10, 2024
Priority date	Dec 1, 2023
Publication date	Mar 17, 2026
Grant date	Mar 17, 2026

Abstract

A circuitry, method, computer storage medium, and terminal for deskew processing include: receiving data lanes, clock signal lanes, deskew control modules, and deskew modules. The receiving data lane receives input data signals, which are in alternating standard sequence. The clock signal lane receives input clock signals. The deskew control module is connected to the receiving data lane and is set to acquire the sample data obtained by sampling the data signal of the data signal lane by the clock signal of the clock signal lane with a preset duration, and determine the delay information based on the sample data. The deskew module is connected to the deskew control module and is set to adjust the phase offset of both the clock signal and the data signal based on the delay information. The embodiments of the present invention sample the data signal and determine the delay information by the deskew control module, adjust the phase offset by the delay information, simplifying the circuitry composition of phase calibration.

First claim

What is claimed is:

1 . A circuitry for deskew processing, comprising:
receiving data lane, clock signal lane, deskew control module, and deskew module, wherein the receiving data lane is set to receive input data signals, which are in alternating standard sequence; wherein the clock signal lane is set to receive input clock signals; wherein the deskew control module is connected to the receiving data lane and is set to acquire sample data obtained by sampling the data signal of the data signal lane by the clock signal of the clock signal lane with a preset duration, and determine the delay information based on the sample data; wherein the deskew module is connected to the deskew control module and is set to adjust the phase offset of both the clock signal and the data signal based on the delay information determined by the deskew control module.

2 . The circuitry of claim 1 , wherein the deskew control module comprises a sample unit and a delay determination unit,
wherein the sample unit is set to acquire the sample data obtained by sampling the data signal of the receiving data signal lane by the clock signal of the clock signal lane with a preset duration; wherein the delay determination unit is set to count and accumulate the number of 0 and 1 in the sample data of the rising edge, as well as the number of 0 and 1 in the sample data of the falling edge according to a preset accumulation period based on the sample data; determine the delay information according to the statistics results of the counting and accumulation; wherein the accumulation period is determined by a preset statistical threshold.

3 . The circuitry of claim 2 , wherein the delay determination unit is set to count and accumulate the number of 0 and 1 in the sample data of the rising edge, as well as the number of 0 and 1 in the sample data of the falling edge according to a preset accumulation period, each counting and accumulation statistics comprises:
When the counting and accumulation statistics value of 0 and/or 1 in the sample data of the rising edge reaches the statistical threshold, the counting and accumulation statistics of the rising edge ends; and When the counting and accumulation statistics value of 0 and/or 1 in the sample data of the falling edge reaches the statistical threshold, the counting and accumulation statistics of the rising edge ends.

4 . The circuitry of claim 3 , wherein the delay determination unit is set to determine the delay information based on the statistics results of the counting and accumulation, comprising:
Upon each determination that the counting and accumulation statistics of the rising edge have ended, the following processing is performed: determine the data corresponding to the rising edge based on the statistics result of the counting and accumulation of the rising edge; record the determined data corresponding to the rising edge, and when the recorded data reaches a preset length, detect the rising edge based on the data corresponding to the rising edge; determine the current sampling location of each detected rising edge; when the number of detected rising edges is greater than or equal to the preset quantity, determine the delay information of the rising edge based on the determined current sampling location of the rising edge; and Upon each determination that the counting and accumulation statistics of the falling edge have ended, the following processing is performed: determine the data corresponding to the falling edge based on the statistics result of the counting and accumulation of the falling edge; record the determined data corresponding to the falling edge, and when the recorded data reaches a preset length, detect the falling edge based on the data corresponding to the falling edge; determine the current sampling location of each detected falling edge; when the number of detected falling edges is greater than or equal to the preset quantity, determine the delay information of the falling edge based on the determined current sampling location of the falling edge.

5 . The circuitry of claim 4 , wherein the delay determination unit is set to determine the data corresponding to the rising edge based on the statistics results of the counting and accumulation for the rising edge, comprising:
Upon the counting and accumulation statistics have ended, if the counting and accumulation statistics value of 0 in the sample data of the rising edge reaches the preset statistical threshold, then determine the data corresponding to the rising edge is 0; Upon the counting and accumulation statistics have ended, if the counting and accumulation statistics value of 1 in the sample data of the rising edge reaches the statistical threshold, or both of the counting and accumulation statistics value of 0 and 1 in the sample data of the rising edge reaches the statistical threshold, then determine the data corresponding to the rising edge is 1.

6 . The circuitry of claim 4 , wherein the delay determination unit is set to determine the data corresponding to the falling edge based on the statistics results of the counting and accumulation for the falling edge, comprising:
Upon the counting and accumulation statistics have ended, if the counting and accumulation statistics value of 0 in the sample data of the falling edge reaches the preset statistical threshold, then determine the data corresponding to the falling edge is 0; and Upon the counting and accumulation statistics have ended, if the counting and accumulation statistics value of 1 in the sample data of the falling edge reaches the statistical threshold, or both of the counting and accumulation statistics value of 0 and 1 in the sample data of the falling edge reaches the statistical threshold, then determine the data corresponding to the falling edge is 1.

7 . The circuitry of claim 4 ,
wherein, the current sampling location of the rising edge is the current sampling location of the second-to-last data in the data corresponding to the rising edge of the preset length; wherein, the current sampling location of the falling edge is the current sampling location of the second-to-last data in the data corresponding to the falling edge of the preset length; wherein both of the initial value of the current sampling location of the data corresponding to rising edge and falling edge are 0; Upon each determination of data corresponding to one rising edge, a preset minimum delay step, Least Significant Bit (LSB), will be added to the current sampling location of the data corresponding to the previous rising edge to obtain the current sampling location of the current data; Upon each determination of data corresponding to one falling edge, an LSB will be added to the current sampling location of the data corresponding to the previous falling edge to obtain the current sampling location of the current data.

8 . The circuitry of claim 4 , wherein the delay determination unit is set to determine the delay information of the rising edge based on the determined current sampling location of the rising edge, comprising:
when the number of detected rising edges is greater than or equal to the preset quantity, and the current sampling location of each rising edge is less than or equal to the preset maximum sampling position threshold, calculate the average of the current sampling locations of the two rising edges among the detected rising edges of preset quantity; Add the averaged result to the preset offset and perform the first limiting processing based on the maximum sampling position threshold; Use the result of the first limiting processing as the delay information of the rising edge.

9 . The circuitry of claim 8 , wherein the delay determination unit is set to

Assignees

• Gowin Semiconductor Corp

Inventors

• Zhou Qiang
• Bai Ruixia
• Lin Xiaozhi
• Wu Qiming
• Sun Yu
• Ding Jia
• Ding Xu

Classifications

• H04L7/033 Primary

  using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop · CPC title

• H04L7/0037 Primary

  Delay of clock signal · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F2213/0002

  Serial port, e.g. RS232C · CPC title

• G06F13/4068

  Electrical coupling · CPC title