Reception circuit

Patent metadata

Field	Value
Publication number	US-9300461-B2
Application number	US-201314420721-A
Country	US
Kind code	B2
Filing date	Sep 12, 2013
Priority date	Sep 18, 2012
Publication date	Mar 29, 2016
Grant date	Mar 29, 2016

Abstract

In a reception circuit, in a first operating mode, the operation of at least a first charge pump circuit of a phase frequency comparator, the first charge pump circuit, samplers other than a specific sampler in samplers provided in a multi-phase sampler, and a data reproducing unit stops. In a second operating mode, the operation of at least a second charge pump circuit of a phase comparator and the second charge pump circuit stops.

First claim

The invention claimed is:

1. A reception circuit comprising:
a frequency tracking loop including a voltage controlled oscillator that outputs multi-phase clock signals having an oscillation frequency corresponding to a control voltage and shifted by equal phase, a phase frequency comparator that compares a phase of a predetermined clock signal of the multi-phase clock signals with a phase of a reference clock signal, a first charge pump circuit that outputs a current corresponding to a comparison result of the phase-frequency comparator, and a loop filter that generates a control voltage applied to the voltage controlled oscillator in response to the current;
a multi-phase sampler having at least one sampler and sampling a transmitted data signal by the multi-phase clock signals;
a data reproducing unit temporarily holding the sample data sampled by the multi-phase sampler and extracting the sample data at a position shifted by a predetermined width from a data boundary position of the data signal;
a phase comparator having a sampler, comparing the phase of the data signal with the phase of a specific clock signal supplied to the specific sampler using output data of the specific sampler among the samplers provided in the multi-phase sampler and output data of a sampler provided in the phase comparator, and reproducing data from the data signal; and
a second charge pump circuit outputting a current corresponding to the comparison result of the phase of the phase comparator to the loop filter,
when in a first operating mode, the operation of at least the first charge pump circuit of the phase frequency comparator, the first charge pump circuit, the samplers other than the specific sampler provided in the multi-phase sampler, and the data reproducing unit stops, and when in a second operating mode, the operation of at least the second charge pump circuit of the phase comparator and the second charge pump circuit stops.

2. The reception circuit according to claim 1 , wherein
the voltage controlled oscillator outputs the multi-phase clock signals of the number equal to the number of phases are each shifted by an equal phase,
the multi-phase sampler includes the samplers of the number equal to the number of phases sampled by the respective multi-phase clock signals,
the specific sampler is a first sampler that sets a first clock signal that is an arbitrary one of the multi-phase clock signals as the specific clock signal, and sets the first clock signal as a sampling clock,
the phase comparator includes:
a second sampler sampling the output data of the first sampler with a second clock signal that has a phase difference of 180 degrees with respect to the first clock signal, a first logic circuit outputting a command signal for advancing the phase of the first clock signal in a duration when the data signal mismatches the output data of the first sampler, and
a second logic circuit outputting a command signal for delaying the phase of the first clock signal in a duration when the output of the first sampler mismatches the output data of the second sampler, and

the output data of the first sampler is set as the reproduction data.

3. The reception circuit according to claim 1 , wherein
the voltage controlled oscillator outputs the multi-phase clock signals of the number equal to the number of phases each shifted by an equal phase,
the multi-phase sampler includes the samplers of the number equal to the number of phases sampled by the respective multi-phase clock signals,
the specific sampler includes a first sampler that sets a first clock signal that is an arbitrary one of the multi-phase clock signals as the specific clock signal, and sets the first clock signal as a sampling clock, and a second sampler that sets a second clock signal having a phase difference of 180 degrees with respect to the first clock signal among the multi-phase clock signals as a sampling clock,
the phase comparator includes:
a third sampler sampling the output data of the first sampler with the first clock signal,
a fourth sampler sampling the output data of the second sampler with the first clock signal,
a first logic circuit outputting a comparison result that the phase of the first clock signal is advanced if it is detected that the output data of the first sampler mismatches the output data of the fourth sampler, and
a second logic circuit outputting a comparison result that the phase of the first clock signal is delayed if it is detected that the output data of the third sampler mismatches the output data of the fourth sampler, and

the output data of the first sampler or the third sampler is set as the reproduction data.

4. The reception circuit according to claim 1 , wherein
the loop filter is configured for setting different filter constants between the first operating mode and the second operating mode.

5. The reception circuit according to claim 4 , wherein
the loop filter includes one or a plurality of capacitors and resistors, and a changeover switch that is connected in series with or in parallel to a part of the one or the plurality of capacitors and resistors, and turns on and off according to the particular operating mode.

6. A reception circuit comprising:
a frequency tracking loop including a first voltage controlled oscillator that outputs a first clock signal having an oscillation frequency corresponding to a control voltage, a phase frequency comparator that compares a phase of the first clock signal with a phase of a reference clock signal, a first charge pump circuit that outputs a current corresponding to a comparison result of the phase-frequency comparator, and a loop filter that generates a control voltage applied to the first voltage controlled oscillator in response to the current;
a second voltage controlled oscillator having a gate terminal, performing oscillation operation having an oscillation frequency corresponding to the control voltage output from the loop filter on the condition that a signal having a permission level is input to the gate terminal, and outputting a second clock signal;
an edge detector outputting an edge detection signal that has the permission level upon detecting an edge of the transmitted data signal;
a selector outputting the signal that has the permission level to the gate terminal in a first operating mode, and outputting an edge detection signal from the edge detector to the gate terminal in a second operating mode;
a phase comparator having a sampler that samples the data signal with the second clock signal, being configured for comparing the phase of the data signal with the phase of the second clock signal, and reproducing data from the data signal; and
a second charge pump circuit outputting a current corresponding to a comparison result of the phases in the phase comparator to the loop filter,
when in the first operating mode, the operation of at least the first charge pump circuit of the phase frequency comparator, the first charge pump circuit, the first voltage controlled oscillator, and the edge detector stops, and when in the second operating mode, the operation of the second charge pump circuit stops.

7. The reception circuit according to claim 6 ,
wherein the phase comparator includes:
a first sampler sampling the data signal with the second clock signal;
a second sampler sampling the output data of the first sampler with a third clock signal that has a phase difference of 180 degrees with respect to the second clock signal;
a first logic circuit outputting a command signal for advancing the phase of the second clock signal in a duration when the data signal mismatches the output data of the first sampler; and
a second logic circuit outputting a command signal for delaying the phase of the secon

Assignees

• Denso Corp

Inventors

• Akita Hironobu
• Ohtsuka Shigeki

Classifications

• H04L7/0331

  with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence) · CPC title

• H04L7/0337

  Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals · CPC title

• H03L7/087 Primary

  using at least two phase detectors or a frequency and phase detector in the loop · CPC title

• H04L7/0087 Primary

  Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection · CPC title

• H03L7/22

  using more than one loop · CPC title