Integrated circuit packages with on package memory architectures

Patent metadata

Field	Value
Publication number	US-12575448-B2
Application number	US-202117483670-A
Country	US
Kind code	B2
Filing date	Sep 23, 2021
Priority date	Sep 23, 2021
Publication date	Mar 10, 2026
Grant date	Mar 10, 2026

Abstract

Integrated circuit (IC) packages with On Package Memory (OPM) architectures are disclosed herein. An example IC package includes a substrate having a first side and a second side opposite the first side, a semiconductor die mounted on the first side of the substrate, and a die pad on the first side of the substrate. The die is electrically coupled to the die pad. The IC package also includes a memory pad on the first side of the substrate. The memory pad is to be electrically coupled to a memory mounted on the first side of the substrate. The IC package further includes a ball on the second side of the substrate, and a memory interconnect in the substrate electrically coupling the die pad, the memory pad, and the ball.

First claim

What is claimed is:

1 . An integrated circuit (IC) package comprising:
a substrate having a first surface and a second surface opposite the first-side surface; a semiconductor die on the first surface of the substrate; a die pad on the first surface of the substrate, the semiconductor die electrically coupled to the die pad; a memory pad on the first surface of the substrate, the memory pad to be electrically coupled to a memory to be mounted on the first side surface of the substrate, the memory pad and the die pad in a same plane parallel to the first surface; a ball on the second surface of the substrate; and a single memory interconnect in the substrate electrically coupling the die pad, the memory pad, and the ball, the memory interconnect including a straight line of conductive material extending completely through the substate from the memory pad on the first surface of the substrate and to the ball on the second surface of the substrate.

2 . The IC package of claim 1 , including a trace and a via that electrically couple the die pad and the line of conductive material.

3 . The IC package of claim 1 , wherein the die pad is one of a plurality of die pads on the first surface of the substrate, and the memory pad is one of a plurality of memory pads on the first surface of the substrate, and the ball is one of a plurality of balls on the second surface of the substrate and the single memory interconnect is one of a plurality of memory interconnects in the substrate, respective ones of the plurality of memory interconnects electrically coupling a corresponding one of the die pads, a corresponding one of the memory pads, and a corresponding one of the balls.

4 . The IC package of claim 1 , including an integrated heat spreader (IHS) on the first surface of the substrate and at least partially covering the semiconductor die.

5 . An assembly comprising:
a circuit board; and the IC package of claim 1 mounted on the circuit board.

6 . The assembly of claim 5 , including a memory mounted on the first side surface of the substrate, the memory electrically coupled to the memory pad.

7 . The assembly of claim 5 , including:
a first pad on the circuit board, the ball electrically coupled to the first pad; a second pad on the circuit board; a memory on the circuit board such that the memory is electrically coupled to the second pad; and an interconnect in the circuit board to electrically couple the first pad and the second pad.

8 . The assembly of claim 5 , including:
a first pad on the circuit board, the ball electrically coupled to the first pad; a second pad on the circuit board; a Small Outline Dual In-line Memory Module (SODIMM) on the circuit board such that the SODIMM is electrically coupled to the second pad; and an interconnect to in the circuit board to electrically couple the first pad and the second pad.

9 . The IC package of claim 6 , wherein the memory is a digital random-access memory (DRAM).

10 . The assembly of claim 6 , wherein the ball on the second side surface of the substrate does not engage a contact on the circuit board.

11 . A method comprising:
fabricating a package substrate; adding a memory pad on a first side of the package substrate, the memory pad exposed on the first side of the package substrate; adding a die pad on the first side of the package substrate, the die pad exposed on the first side of the package substrate; adding a ball on a second side of the package substrate opposite the first side; adding a stack of stubs through the package substrate between the first and second sides to electrically couple the memory pad and the ball, the stack of stubs in a single line and extending completely through the package substrate between the memory pad and the ball; and adding a trace in the package substrate that branches off of the stack of stubs and is electrically coupled to the die pad to electrically couple the die pad, the memory pad, and the ball, the stack of stubs providing the only path through the package substrate that electrically couples the die pad to the second side of the package substrate.

12 . The method of claim 11 , including mounting a die on the first side of the package substrate such that the die is electrically coupled to the die pad.

13 . An integrated circuit (IC) package comprising:
a substrate having a first side and a second side opposite the first side; memory pads on the first side of the substrate, the memory pads to be electrically coupled to a memory mounted on an exterior surface of the first side of the substrate, the memory pads in a first pattern and spacing to be mechanically coupled directly to balls on the memory; die pads on the first side of the substrate, the die pads to be electrically coupled to a semiconductor die mounted on the exterior surface of the first side of the substrate; balls on the second side of the substrate; and vias in the substrate electrically coupling corresponding ones of the memory pads and the balls, the vias extending in substantially parallel lines through the substrate such that a second pattern and spacing of the balls on the second side of the substrate is the same as the first pattern and spacing of the memory pads on the first side of the substrate, a first one of the die pads electrically coupled to a first one of the vias that electrically couples a corresponding first one of the memory pads to a corresponding first one of the balls, the first one of the die pads electrically coupled to the second side of the substrate exclusively through the first one of the vias.

14 . The IC package of claim 13 , wherein the vias are stacks of stubs in layers of the substrate.

15 . The IC package of claim 13 , wherein the vias form part of memory interconnects, respective ones of the memory interconnects electrically couple corresponding ones of the memory pads, corresponding ones of the balls, and corresponding ones of the die pads.

16 . The IC package of claim 13 , including the memory mounted on the first side of the substrate and electrically coupled to the memory pads.

17 . The IC package of claim 13 , wherein respective ones of the vias include a single stack of stubs connecting one of the memory pads on the first side and one of the balls on the second side.

18 . The IC package of claim 13 , wherein the balls are first balls, and the IC package includes second balls distributed along the second side of the substrate, the second balls to electrically couple the semiconductor die to a circuit board, the first balls to be electrically isolated from contacts on the circuit board when the second balls are electrically coupled to the circuit board.

19 . The IC package of claim 18 , wherein the first balls are distributed across a first area of the second surface, and the second balls are distributed across a second area of the second surface, the second area spaced apart from the first area, the first area equivalent to a third area across which the memory pads are distributed, the second area larger than a fourth area across which the die pads are distributed.

20 . The IC package of claim 1 , wherein the ball is a first ball, and the memory is to be mounted on the first surface of the substrate spaced apart from and beside the semiconductor die, the IC package including:
a second ball on the second surface of the substrate; and a die interconnect in the substrate electrically coupling the semiconductor die to the second ball.

Assignees

• Intel Corp

Inventors

• Goh Eng Huat
• Chang Mooi Ling
• Khoo Poh Boon
• Lim Chu Aun
• Lim Min Suet
• Ranjan Prabhat

Classifications

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W40/226

  characterised by projecting parts, e.g. fins to increase surface area (leadframes for cooling H10W70/461) · CPC title