Power semiconductor module

Patent metadata

Field	Value
Publication number	US-12575430-B2
Application number	US-202118028098-A
Country	US
Kind code	B2
Filing date	Sep 23, 2021
Priority date	Oct 15, 2020
Publication date	Mar 10, 2026
Grant date	Mar 10, 2026

Abstract

The invention relates to a power semiconductor module comprising a conductive base, a conductive top, and at least two power semiconductor devices arranged between the conductive base and the conductive top. The semiconductor devices are each configured for a current of at least 1 A and/or for a voltage of at least 50 V. An insulating spacer layer is arranged on the power semiconductor devices and at least partially between the conductive base and the conductive top. At least two vertical connection elements pass from the power semiconductor devices through the spacer layer and conductively connect the conductive top with the power semiconductor devices. The spacer layer and the vertical connection elements are configured for compensating height differences of the power semiconductor devices.

First claim

The invention claimed is:

1 . A power semiconductor module comprising
at least one conductive base, at least one conductive top, at least two power semiconductor devices arranged between the at least one conductive base and the at least one conductive top, the semiconductor devices are each configured for a current of at least 1 A and/or for a voltage of at least 50 V, an insulating spacer layer arranged on the power semiconductor devices and at least partially between the at least one conductive base and the at least one conductive top, and at least two vertical connection elements passing from the power semiconductor devices through the spacer layer and conductively connecting the at least one conductive top with each of the power semiconductor devices, wherein
the spacer layer and the vertical connection elements are configured for compensating height differences of the power semiconductor devices,
the spacer layer comprises at least two insulating sub-layers arranged one above the other, an electric wiring is provided between the at least two insulating sub-layers,
on a side of the electric wiring facing the power semiconductor devices as well as on a side of the electric wiring remote from the power semiconductor devices and through each one of the at least two insulating sub-layers, there is at least one of the at least two vertical connection elements, and
the spacer layer is directly arranged on the at least two power semiconductor devices and on the conductive base and extends laterally on both front sides beyond the conductive base, and the at least one conductive top is arranged directly on top of the vertical connection elements and directly on the spacer layer.

2 . The power semiconductor module of the previous claim 1 ,
wherein the at least one conductive base and the at least one conductive top respectively define two parallel mounting planes, and wherein the spacer layer protrudes laterally from the at least one conductive base and the at least one conductive top and terminates flush with the mounting planes in a direction perpendicular with the mounting planes.

3 . The power semiconductor module of claim 1 , comprising a gate conductor connected to respective gates of the power semiconductor devices and embedded within the spacer layer.

4 . The power semiconductor module of claim 1 , wherein the sub-layers each include fibers and a matrix material.

5 . The power semiconductor module of claim 1 , comprising a conductive base plate and a conductive top plate, whereby the at least one conductive base is arranged on the base plate and the top plate is conductively arranged on the at least one conductive top, so that the at least one conductive base, the at least one conductive top, and the spacer layer are sandwiched between the base plate and the top plate.

6 . The power semiconductor module of claim 5 , whereby at least one of the base plate and the top plate comprise a cooling channel for cooling the power semiconductor devices.

7 . The power semiconductor module of claim 1 ,
wherein there is exactly one conductive base carrying all the power semiconductor devices, and wherein there is exactly one conductive top, wherein at least one of the conductive base and the conductive top comprises at least one of Cu, Mo, Fe, Ni, Al, and Co.

8 . The power semiconductor module of claim 1 , comprising at least one of
at least two of the conductive bases and at least two of the conductive tops separated from each other and each associated to at least one of the power semiconductor devices, wherein between adjacent conductive bases and/or conductive tops, respectively, along a lateral direction there is only the spacer layer.

9 . The power semiconductor module of claim 1 , comprising at least one of
at least one creepage distance enhancer arranged at at least one lateral side of the spacer layer and the spacer layer having a passivation coating.

10 . The power semiconductor module of claim 1 , wherein the spacer layer directly adjoins the at least one conductive base, the at least one conductive top, each one of the power semiconductor devices and each one of the vertical connection elements.

11 . The power semiconductor module of claim 1 ,
wherein the at least one conductive base comprises at least one recess whereas in total there is a plurality of the recesses, and wherein the power semiconductor devices are each partially or completely located in one of the recesses so that there is a one-to-one assignment between the recesses and the power semiconductor devices.

12 . A power semiconductor stack comprising a plurality of the power semiconductor modules of claim 1 arranged one above the other, wherein the power semiconductor modules are pressed together with a pressure of at least 0.5 kN/cm2.

13 . A method for manufacturing a power semiconductor module comprising the steps of
conductively bonding at least two power semiconductor devices on at least one conductive base, the semiconductor devices are each configured for a current of at least 1 A and/or for a voltage of at least 50 V, arranging an insulating spacer layer on the power semiconductor devices and on the at least one conductive base, passing thereafter at least two vertical connection elements through the spacer layer or attaching, prior to arranging the spacer layer, bond spacers as the vertical connection elements to the power semiconductor devices, for conductively connecting each of the power semiconductor devices thereby compensating possible height differences of the power semiconductor devices, and arranging at least one conductive top on the spacer layer and conductively on the vertical connection elements, wherein
the spacer layer comprises at least two insulating sub-layers arranged one above the other, an electric wiring is provided between the at least two insulating sub-layers,
on a side of the electric wiring facing the power semiconductor devices as well as on a side of the electric wiring remote from the power semiconductor devices and through each one of the at least two insulating sub-layers, there is at least one of the at least two vertical connection elements, and
the spacer layer is directly arranged on the at least two power semiconductor devices and on the conductive base and extends laterally on both front sides beyond the conductive base, and the at least one conductive top is arranged directly on top of the vertical connection elements and directly on the spacer layer.

14 . The method according to claim 13 , comprising the steps of
conductively arranging the at least one conductive base with the power semiconductor devices, the at least two vertical connection elements and the at least one conductive top on a conductive base plate that is configured for cooling the power semiconductor devices, and conductively arranging a conductive top plate on the at least one conductive top, wherein electrical contacts between the base plate and the at least one conductive base, and between the top plate and the at least one conductive top, respectively, are dry contacts.

15 . The method according to claim 13 , comprising the steps of arranging the at least two insulating sub-layers on top of each other to create the spacer layer, the sub-layers are prepregs.

16 . The method of claim 13 , wherein the at least one conductive base and the at least one conductive top respectively define two parallel mounting planes, and wherein the spacer layer protrudes laterally from the at least one conductive base and the at least one conductive top and ter

Assignees

• Hitachi Energy Ltd

Inventors

• Schuderer Juergen
• Liu Chunlei
• Kicin Slavo
• Salvatore Giovanni
• Mohn Fabian

Classifications

• H10W72/30

  Die-attach connectors · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/5475

  multiple bond wires connected to common bond pads at both ends of the wires · CPC title