Apparatus and method for sigma-delta modulator quantization noise cancellation

Patent metadata

Field	Value
Publication number	US-12574047-B2
Application number	US-202418673969-A
Country	US
Kind code	B2
Filing date	May 24, 2024
Priority date	Jul 20, 2022
Publication date	Mar 10, 2026
Grant date	Mar 10, 2026

Abstract

Described herein is a fractional phase locked loop with sigma-delta modulator (SDM) quantization noise cancellation. The fractional phase includes a digital filter configured to receive an error signal based on a comparison of a reference clock and a feedback clock, a controlled oscillator configured to generate an output clock by adjusting a frequency of the controlled oscillator based on a control signal output by the digital filter, the feedback clock being based on the output clock, a sigma-delta modulator configured to control division of the output clock to generate a divided output clock which includes a sigma-delta modulator quantization noise and a digital-to-time converter configured to receive a cancellation code from an integrator in the sigma-delta modulator and cancel the sigma-delta modulator quantization noise in the divided output clock with the cancellation code to generate the feedback clock.

First claim

What is claimed is:

1 . A digital-to-time converter, comprising:
a first circuit configured to receive a cancellation code; and a second circuit configured to receive a clock embedded with a quantization noise due to a sigma-delta modulator, wherein the cancellation code is tapped over time from an internal integrator of the sigma-delta modulator and is proportional to the quantization noise due to the sigma-delta modulator, wherein the first circuit and the second circuit are collectively configured to phase align and cancel the quantization noise with the cancellation code to generate an output clock, wherein the digital-to-time converter has a cancellation point based on setting a resistor-capacitor constant of the digital-to-time converter to a controlled oscillator target period and implementing to a defined voltage, and wherein voltage based changes in the cancellation point are tracked using a least means square algorithm which uses a statistical output from a digital filter in a phase locked loop.

2 . The digital-to-time converter of claim 1 , wherein the first circuit includes a capacitor array digitally controlled by the cancellation code to obtain a desired phase delay for substantially matching the quantization noise.

3 . The digital-to-time converter of claim 1 , further comprising a third circuit configured to compensate for the voltage based changes in the cancellation point.

4 . The digital-to-time converter of claim 1 , further comprising a reset circuit configured to reset the digital-to-time converter to a zero voltage value for each cancellation code.

5 . The digital-to-time converter of claim 1 , wherein the first circuit and the second circuit use one edge of the clock to reset the digital-to-time converter to remove memory effects for each cancellation code and another edge of the clock to substantially phase align the quantization noise with the cancellation code.

6 . A method for improved quantization noise cancellation, the method comprising:
receiving, at a digital-to-time converter, a cancellation code from a sigma-delta modulator and a clock embedded with a quantization noise due to the sigma-delta modulator, wherein the cancellation code is tapped over time from an internal integrator of the sigma-delta modulator and is proportional to the quantization noise due to the sigma-delta modulator; resetting, by the digital-to-time converter, the digital-to-time converter by using one edge of the clock to remove memory effects for each cancellation code; substantially phase aligning, by the digital-to-time converter, the cancellation code with the quantization noise by using another edge of the clock; and cancelling, by the digital-to-time converter, the quantization noise from the clock.

7 . The method of claim 6 , further comprising
providing a cancellation point based on setting a resistor-capacitor constant to a controlled oscillator target period and implementing to a defined voltage.

8 . The method of claim 6 , further comprising
compensating for voltage based changes in a cancellation point by comparing a quantization noise cancelled clock with a reference voltage which tracks the voltage based changes.

9 . The method of claim 8 , wherein the voltage based changes are tracked using a least means square algorithm which uses a statistical output from a digital filter.

10 . The method of claim 6 , wherein the substantially phase aligning further comprising
digitally controlling a capacitor array by the cancellation code to achieve a desired phase delay of the cancellation code to substantially match a phase of the quantization noise.

11 . The method of claim 6 , wherein the resetting resets the digital-to-time converter to a zero voltage value for each cancellation code.

12 . The method of claim 6 , wherein the cancellation code is tapped from a first internal integrator of the sigma-delta modulator.

13 . A digital-to-time converter, comprising:
a circuit configured to receive a cancellation code from a sigma-delta modulator and a clock embedded with a quantization noise due to the sigma-delta modulator, wherein the cancellation code is tapped over time from an internal integrator of the sigma-delta modulator and is proportional to the quantization noise due to the sigma-delta modulator; a reset circuit configured to reset the digital-to-time converter by using one edge of the clock to remove memory effects for each cancellation code; and the circuit further configured to substantially phase align the cancellation code with the quantization noise by using another edge of the clock and cancel the quantization noise from the clock.

14 . The digital-to-time converter of claim 13 , wherein the circuit includes a cancellation point based on setting a resistor-capacitor constant to a controlled oscillator target period and implementing to a defined voltage.

15 . The digital-to-time converter of claim 13 , wherein the circuit further comprising
a compensation circuit configured to compensate for voltage based changes in a cancellation point by comparing a quantization noise cancelled clock with a reference voltage which tracks the voltage based changes.

16 . The digital-to-time converter of claim 15 , wherein the voltage based changes are tracked using a least means square algorithm which uses a statistical output from a digital filter.

17 . The digital-to-time converter of claim 13 , wherein the circuit digitally controls a capacitor array by the cancellation code to achieve a desired phase delay of the cancellation code to substantially match a phase of the quantization noise.

18 . The digital-to-time converter of claim 13 , wherein the reset circuit resets the digital-to-time converter to a zero voltage value for each cancellation code.

19 . The digital-to-time converter of claim 13 , wherein the circuit is further configured to receive the cancellation code from a first internal integrator of the sigma-delta modulator.

20 . The digital-to-time converter of claim 1 , wherein the internal integrator is configured to accumulate, over time, a difference between a frequency control word and an output of the sigma-delta modulator to generate the cancellation code.

Assignees

• Ciena Corp

Inventors

• Wen Tingjun
• Aouini Sadok
• Ben-Hamida Naim
• Mikkelsen Matthew
• Shalmani Soheyl Ziabakhsh
• Honarparvar Mohammad

Classifications

• H03M3/50 Primary

  Digital/analogue converters using delta-sigma modulation as an intermediate step (digital delta-sigma modulators per se H03M7/3004) · CPC title

• H03M3/454

  with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage · CPC title

• H03M3/43

  the quantiser being a single bit one · CPC title

• H03M3/424

  the quantiser being a multiple bit one · CPC title

• H03L7/1976

  using a phase accumulator for controlling the counter or frequency divider · CPC title