Dummy Metal-Insulator-Metal Structures Within Vias
US-2023352396-A1 · Nov 2, 2023 · US
US12573553B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12573553-B2 |
| Application number | US-202318519346-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 27, 2023 |
| Priority date | Nov 27, 2023 |
| Publication date | Mar 10, 2026 |
| Grant date | Mar 10, 2026 |
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The technology described herein is directed towards a capacitor with a modified design (relative to standard capacitors), in which a first conductor is coupled to a second conductor via a distributed array of conducting interconnects through a dielectric that separates the conductors. The array of interconnects facilitates electrical surface current flow between the first conductor and the second conductor, and determines the self-resonant frequency of the capacitor. The array (or enlarged area) of conducting interconnects, not present in standard capacitors, results in capacitors with larger self-resonant frequency, e.g., having a substantially stable capacitance over a range of high radio frequencies, including millimeter wave frequencies. This further provides an improved quality factor. The improvements resulting from the technology described herein facilitate more optimal surface current density. The modified capacitor provides benefits in various circuits, e.g., in an impedance or a millimeter wave frequency phase shifter for antenna elements.
Opening claim text (preview).
What is claimed is: 1 . A capacitor device, comprising: a first conductor; a second conductor; and a dielectric layer between the first conductor and the second conductor, the dielectric layer coupled to an interconnect overlapping area to facilitate electrical surface current flow between the first conductor and the second conductor, wherein the interconnect overlapping area is configured to determine a resonance frequency of the capacitor device, and wherein the interconnect overlapping area comprises a single elongated via, and wherein the single elongated via determines an overall size of the interconnect overlapping area. 2 . The capacitor device of claim 1 , wherein the interconnect overlapping area is positioned proximate to a periphery of a radio frequency ground plane of the capacitor device. 3 . The capacitor device of claim 1 , wherein the interconnect overlapping area is substantially centered substantially opposite a signal port of the capacitor device. 4 . The capacitor device of claim 1 , wherein the single elongated via determines an overall size of the interconnect overlapping area. 5 . The capacitor device of claim 1 , wherein the single elongated via is shaped in a circular or substantially circular shape. 6 . The capacitor device of claim 1 , wherein the single elongated via is proximate to a periphery of the first conductor. 7 . The capacitor device of claim 1 , wherein the single elongated via is proximate to less than one half of a periphery of the first conductor. 8 . The capacitor device of claim 1 , wherein the single elongated via is proximate to more than one half of a periphery of the first conductor. 9 . A device, comprising: a first conductor electrode separated from a second conductor electrode by a dielectric medium to operate as a metal-insulator-metal capacitor with a radio frequency ground plane; and an interconnect overlapping area aligned with a periphery of the radio frequency ground plane to facilitate electrical surface current flow between the first conductor and the second conductor to reduce a surface current density of the metal-insulator-metal capacitor, wherein a resonance frequency of the capacitor device is based on a size of the interconnect overlapping area, wherein the interconnect overlapping area comprises a single via proximate to part of a periphery of the first conductor, wherein the single via covers at least a threshold large area with respect to current flow between the conductors, and wherein the single via determines an overall size of the interconnect overlapping area. 10 . The device of claim 9 , wherein the first conductor electrode extends to cover the radio frequency ground plane. 11 . The device of claim 9 , wherein the interconnect overlapping area enables electrical vias from the first conductor electrode to the second conductor electrode through the dielectric medium. 12 . The device of claim 9 , wherein the dielectric medium comprises a first dielectric medium, and wherein the device further comprises a third conductor electrode separated from the second conductor electrode by a second dielectric medium. 13 . The device of claim 9 , wherein the metal-insulator-metal capacitor operates with substantially stable capacitance with frequencies ranging from about one gigahertz to about twenty gigahertz. 14 . A capacitor, comprising: a first conductor overlapping with a dielectric layer, wherein the dielectric layer overlaps a second conductor, wherein the first conductor is electrically coupled to the second conductor via a single elongated interconnect through an interconnect area of the dielectric layer, and wherein the interconnect area is configured to: facilitate electrical surface current flow between the first conductor and the second conductor, and determine a self-resonant frequency of the capacitor, wherein the interconnect area is substantially centered substantially opposite a signal port of the capacitor. 15 . The capacitor of claim 14 , wherein the first conductor extends over at least a portion of a radio frequency ground plane associated with the capacitor. 16 . The capacitor of claim 14 , wherein the single elongated interconnect is positioned proximate to a periphery of the first conductor. 17 . The capacitor of claim 14 , wherein the capacitor is useable as a tuning element as part of an impedance matching network. 18 . The capacitor of claim 14 , wherein the capacitor comprises a part of a millimeter wave frequency phase shifter applicable to an antenna element. 19 . The capacitor device of claim 1 , wherein the capacitor device is comprised in an antenna element. 20 . The device of claim 9 , wherein the interconnect area is substantially centered substantially opposite a signal port of the capacitor device.
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