Method and apparatus to implement an integrated circuit including both dynamic random-access memory (DRAM) and static random-access memory (SRAM)

Patent metadata

Field	Value
Publication number	US-12572299-B2
Application number	US-202217711394-A
Country	US
Kind code	B2
Filing date	Apr 1, 2022
Priority date	Apr 1, 2022
Publication date	Mar 10, 2026
Grant date	Mar 10, 2026

Abstract

Methods and apparatus to implement an integrated circuit including both dynamic random-access memory (DRAM) and static random-access memory (SRAM). In one embodiment, the integrated circuit comprises a static random-access memory (SRAM) device to store a first portion of data of a processor, a dynamic random-access memory (DRAM) device to store a second portion of the data of the processor, and a memory control circuit to read from both the SRAM and DRAM devices, a first set of bits of a first word to be read from the SRAM device and a second set of bits of the first word to be read from the DRAM device.

First claim

What is claimed is:

1 . An integrated circuit comprising:
a static random-access memory (SRAM) device to store a first portion of data of a processor; a dynamic random-access memory (DRAM) device to store a second portion of the data of the processor; and a memory control circuit to read from both the SRAM and DRAM devices, a first set of bits of a first word to be read from the SRAM device and a second set of bits of the first word to be read from the DRAM device, wherein reading the second set of bits from the DRAM device comprises reading bits from one or more addresses in a first set of addresses first before reading bits from one or more addresses in a second set of addresses, wherein the first set of addresses corresponds to a first region closer to a column input/output circuit of the DRAM device than a second region for the second set of addresses.

2 . The integrated circuit of claim 1 , wherein the first set of bits of the first word includes a plurality of concatenated bits from the SRAM device, the plurality of concatenated bits including an encryption status indication of the second set of bits from the DRAM device.

3 . The integrated circuit of claim 1 , wherein the first set of bits of the first word includes a plurality of concatenated bits from the SRAM device, the plurality of concatenated bits including encryption information of the second set of bits from the DRAM device.

4 . The integrated circuit of claim 1 , wherein a set of most significant bits of the first word is to be read from the SRAM device while a set of less significant bits of the first word is to be read from the DRAM device.

5 . The integrated circuit of claim 1 , wherein the first set of addresses within the DRAM device is to store data that has a first access characteristic while the second set of addresses within the DRAM device is to store data that has a second access characteristic.

6 . The integrated circuit of claim 5 , wherein the first and second access characteristics are a first type of access frequency and a second type of access frequency that is less frequent than the first type, respectively.

7 . The integrated circuit of claim 1 , wherein the read of the first set of bits from the SRAM device is to take fewer clock cycles than the read of the second set of bits from the DRAM device.

8 . The integrated circuit of claim 1 , wherein the memory control circuit is to write to both the SRAM and DRAM devices, a first set of bits of a second word is to be written to the SRAM device and a second set of bits of the second word is to be written to the DRAM device.

9 . The integrated circuit of claim 8 , wherein the second set of bits of the second word is written into a region of memory cell within the DRAM device based on an access characteristic of the second set of bits of the second word.

10 . The integrated circuit of claim 1 , wherein a memory cell within the DRAM device implements a selector transistor using a thin-film transistor (TFT).

11 . A method comprising:
storing a first portion of data of a processor in a static random-access memory (SRAM) device within an integrated circuit; storing a second portion of data of the processor in a dynamic random-access memory (DRAM) device within the integrated circuit; and reading from both the SRAM and DRAM devices, a first set of bits of a first word to be read from the SRAM device and a second set of bits of the first word to be read from the DRAM device, wherein reading the second set of bits from the DRAM device comprises reading bits from one or more addresses in a first set of addresses first before reading bits from one or more addresses in a second set of addresses, wherein the first set of addresses corresponds to a first region closer to a column input/output circuit of the DRAM device than a second region for the second set of addresses.

12 . The method of claim 11 , wherein the first set of bits of the first word includes a plurality of concatenated bits from the SRAM device, the plurality of concatenated bits including an encryption status indication of the second set of bits from the DRAM device and a data bit stored in the DRAM device.

13 . The method of claim 11 , wherein a set of most significant bits of the first word is to be read from the SRAM device while a set of less significant bits of the first word is to be read from the DRAM device.

14 . The method of claim 11 , wherein the first set of addresses within the DRAM device is to store data that has a first access characteristic while the second set of addresses within the DRAM device is to store data that has a second access characteristic.

15 . A non-transitory computer-readable storage medium storing instructions that when executed by a processor of a computing system, are capable of causing the computing system to perform:
storing a first portion of data of the processor in a static random-access memory (SRAM) device within an integrated circuit; storing a second portion of data of the processor in a dynamic random-access memory (DRAM) device within the integrated circuit; and reading from both the SRAM and DRAM devices, a first set of bits of a first word to be read from the SRAM device and a second set of bits of the first word to be read from the DRAM device, wherein reading the second set of bits from the DRAM device comprises reading bits from one or more addresses in a first set of addresses first before reading bits from one or more addresses in a second set of addresses, wherein the first set of addresses corresponds to a first region closer to a column input/output circuit of the DRAM device than a second region for the second set of addresses.

16 . The non-transitory computer-readable storage medium of claim 15 , wherein the read of the first set of bits from the SRAM device is to take fewer clock cycles than the read of the second set of bits from the DRAM device.

17 . The non-transitory computer-readable storage medium of claim 15 , wherein when executed by the processor of the computing system, the instructions are capable of causing the computing system to further perform:
writing to both the SRAM and DRAM devices, a first set of bits of a second word is to be written to the SRAM device and a second set of bits of the second word is to be written to the DRAM device.

18 . The non-transitory computer-readable storage medium of claim 15 , wherein a memory cell within the DRAM device implements a selector transistor using a thin-film transistor (TFT).

Assignees

• Intel Corp

Inventors

• Sharma Abhishek Anil
• Gomes Wilfred
• Ranade Pushkar
• Koduri Rajabali

Classifications

• G06F3/0673

  Single storage device · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F30/337

  Design optimisation · CPC title

• G06F12/0855

  Overlapped cache accessing, e.g. pipeline (G06F12/0846 takes precedence) · CPC title

• G06F12/0886

  Variable-length word access · CPC title