Converting processing dimensions of a wafer package

Patent metadata

Field	Value
Publication number	US-12571971-B2
Application number	US-202519097732-A
Country	US
Kind code	B2
Filing date	Apr 1, 2025
Priority date	Jun 3, 2024
Publication date	Mar 10, 2026
Grant date	Mar 10, 2026

Abstract

The present disclosure relates to packaging techniques in connection with packaging electrical and optical components within circuit packages. For example, one or more examples described herein involve producing or manufacturing wafers having circuit packages formed thereon. Techniques described herein related to modifying a dimension of wafers in order that the wafers conform to a nominal dimension, such that the wafers may be implemented in connection with processing equipment that is specifically configured to operate on wafers of the nominal dimension.

First claim

What is claimed is:

1 . A method of making a wafer structure having a desired base dimension, comprising;
obtaining a photonic integrated circuit (PIC) wafer having a first base dimension, the desired base dimension being larger than the first base dimension, the PIC wafer comprising:
an optical region near a top surface of the PIC wafer configured to allow light to enter and exit the PIC wafer;
optical transmitter and receiver portions in optical communication with the optical region, the optical transmitter and receiver portions having electrical interconnects to the top surface of the PIC wafer in a portion that does not extend into the optical region; and
one or more electronic components including electrical transmitter and receiver portions interconnected with the optical transmitter and receiver portions via electrical interconnects, forming electro-optical paths to and from the one or more electronic components to the optical region;
positioning the PIC wafer on a base plate having a base dimension that is the desired base dimension, wherein the PIC wafer covers only a portion of a top surface of the base plate such that a portion of the top surface of the base plate is exposed around a perimeter of the PIC wafer; and depositing an overmold over the PIC wafer, the one or more electronic components, and the exposed portion of the base plate around the perimeter of the PIC wafer, thereby forming a wafer structure having the desired base dimension; removing a layer of the overmold, thereby exposing the one or more electronic components disposed on the PIC wafer, wherein removing the layer of the overmold exposes an optical path to the optical region near the top surface of the PIC wafer.

2 . The method of claim 1 , further comprising removing the base plate from the wafer structure, thereby releasing the wafer structure from the base plate.

3 . The method of claim 1 , further comprising coupling an optical fiber to a grating coupler in the optical region using an optical interface component.

4 . The method of claim 3 , wherein the optical interface component is a fiber array unit (FAU).

5 . The method of claim 1 , further comprising performing tasks on the wafer structure using processing equipment configured to process wafers having the desired base dimension.

6 . The method of claim 5 , wherein the processing tasks include forming through-silicon vias (TSVs) in the PIC wafer and forming interconnects on the PIC wafer connected to the TSVs for providing electrical power to the one or more electronic components.

7 . The method of claim 1 , wherein a shape of the PIC wafer is a disk having a diameter of approximately eight inches.

8 . The method of claim 7 , wherein a shape of the wafer structure is a disk having a diameter of approximately twelve inches.

9 . The method of claim 1 , wherein the PIC wafer comprises waveguides formed within the PIC wafer and passing between the optical region and the optical transmitter and receiver portions.

10 . The method of claim 1 , wherein the electrical interconnects comprise connections through bumps on the top surface of the PIC wafer; and
the method further comprises disposing the one or more electronic components on the PIC wafer before obtaining the PIC wafer, wherein disposing the one or more electronic components comprises attaching the one or more electronic components to the bumps on the top surface of the PIC wafer.

Assignees

• Celestial Ai Inc

Inventors

• Aggarwal Ankur
• Rathi Anmol
• Pothukuchi Suresh Venkata

Classifications

• G02B6/4215

  the intermediate optical elements being wavelength selective optical elements, e.g. variable wavelength optical modules or wavelength lockers (G02B6/4246 takes precedence) · CPC title

• G02B6/3897

  Connectors fixed to housings, casing, frames or circuit boards (G02B6/44528 takes precedence) · CPC title

• G02B6/4214

  the intermediate optical element having redirecting reflective means, e.g. mirrors, prisms for deflecting the radiation from horizontal to down- or upward direction toward a device (G02B6/4246 takes precedence) · CPC title

• H10W72/30

  Die-attach connectors · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title