Atomic layer deposition bonding for heterogeneous integration of photonics and electronics

Patent metadata

Field	Value
Publication number	US-10168475-B2
Application number	US-201715408725-A
Country	US
Kind code	B2
Filing date	Jan 18, 2017
Priority date	Jan 18, 2017
Publication date	Jan 1, 2019
Grant date	Jan 1, 2019

Abstract

Methods and systems are presented for heterogeneous integration of photonics and electronics with atomic layer deposition (ALD) bonding. One method includes operations for forming a compound semiconductor and for depositing (e.g., via atomic layer deposition) a continuous film of a protection material (e.g., Al 2 O 3 ) on a first surface of the compound semiconductor. Further, the method includes an operation for forming a silicon on insulator (SOI) wafer, with the SOI wafer comprising one or more waveguides. The method further includes bonding the compound semiconductor at the first surface to the SOI wafer to form a bonded structure and processing the bonded structure. The protection material protects the compound semiconductor from acid etchants during further processing of the bonded structure.

First claim

What is claimed is:

1. A method comprising:
forming a compound semiconductor;
depositing a film of protection material on a side of the compound semiconductor using vapor deposition;
forming a silicon on insulator (SOI) wafer, the SOI wafer comprising one or more waveguides;
forming a bonded structure by placing the side of the compound semiconductor on the SOI wafer and applying heat, the side of the compound semiconductor placed such that the film of protection material is in contact with the SOI wafer;
applying acid etchants to the bonded structure, the protection material protecting the side of the compound semiconductor from the acid etchants.

2. The method as recited in claim 1 , wherein the vapor deposition used to deposit the film of the protection material is atomic layer deposition.

3. The method as recited in claim 1 , wherein the protection material is Al 2 O 3 .

4. The method as recited in claim 1 , wherein the compound semiconductor is bonded to a bonding surface of the SOI wafer, and wherein the protection material protects the bonding surface of the SOI wafer from the acid etchants.

5. The method as recited in claim 1 , wherein the film has a height between 2 and 50 nanometers.

6. The method as recited in claim 1 , wherein the compound semiconductor is a III-V wafer.

7. The method as recited in claim 1 , wherein bonding the compound semiconductor to the SOI wafer further comprises:
placing the compound semiconductor on the SOI wafer;
applying pressure and the heat to the compound semiconductor and the SOI wafer; and
removing the pressure and the heat.

8. The method as recited in claim 1 , wherein the SOI wafer includes a SiO 2 layer directly above one of the one or more waveguides, wherein the SiO 2 layer is placed in contact with the side of the compound semiconductor for the bonding.

9. The method as recited in claim 1 , wherein the compound semiconductor does not include a super lattice layer.

10. The method as recited in claim 1 , wherein the applied acid etchants pattern a circuit on the compound semiconductor.

11. A method comprising:
forming a III-V based semiconductor;
layering a film of Al 2 O 3 on sides of the III-V based semiconductor;
singulating the III-V based semiconductor to create a plurality of dies;
plasma cleaning the plurality of dies;
forming a silicon on insulator (SOI) wafer, the SOI wafer comprising one or more waveguides;
placing the sides of the plurality of dies on the SOI wafer such that the film is in contact with the SOI wafer;
bonding, by applying heat, the plurality of dies to the SOI wafer to form a bonded structure; and
applying acid etchants to the bonded structure, the Al 2 O 3 protecting the sides of the plurality of dies from the acid etchants.

12. The method as recited in claim 11 , wherein depositing the film of Al 2 O 3 is performed by atomic layer deposition.

13. The method as recited in claim 11 , wherein bonding the plurality of dies to the SOI wafer further comprises:
applying pressure and heat to the plurality of dies and the SOI wafer; and
removing the pressure and heat.

14. The method as recited in claim 11 , wherein the SOI wafer includes a SiO 2 layer directly above one of the one or more waveguides, wherein the SiO 2 layer is placed in contact with the sides of the plurality of dies.

Assignees

• Juniper Networks Inc

Inventors

• Parker John
• Fish Gregory Alan
• Spannagel Martin A
• Labaro Antonio

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1914 Primary

  using bonding · CPC title

• H10P50/648

  Anisotropic liquid etching · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69395

  the material containing zirconium, e.g. ZrO2 · CPC title