Semiconductor device circuitry formed from remote reservoirs

Patent metadata

Field	Value
Publication number	US-12568869-B2
Application number	US-202318237202-A
Country	US
Kind code	B2
Filing date	Aug 23, 2023
Priority date	Aug 28, 2022
Publication date	Mar 3, 2026
Grant date	Mar 3, 2026

Abstract

This document discloses techniques, apparatuses, and systems for semiconductor device circuitry formed from remote reservoirs. A semiconductor assembly includes a first semiconductor die with a layer of dielectric material having an opening. The first semiconductor die further includes a reservoir of conductive material having a first portion located adjacent to the opening, a second portion remote from the opening, and a third portion coupling the first portion and the second portion. A second semiconductor die includes a layer of dielectric material and a contact pad corresponding to the opening. The reservoir of conductive material is heated to volumetrically expand the second portion into the third portion, the third portion into the first portion, and the first portion through the opening to form an interconnect electrically coupling the first semiconductor die and the second semiconductor die at the contact pad. In this way, a connected semiconductor device may be assembled.

First claim

What is claimed is:

1 . A method of making a semiconductor device assembly, comprising:
providing a first semiconductor die including:
a first layer of dielectric material having an opening; and
a reservoir of conductive material having a first portion located adjacent to the opening, a second portion remote from the opening, and a third portion coupling the first portion and the second portion;
providing a second semiconductor die including:
a second layer of dielectric material; and
a contact pad corresponding to the opening;
aligning the first semiconductor die and the second semiconductor die such that the opening aligns with the contact pad; and heating the reservoir of conductive material effective to cause the second portion to volumetrically expand into the third portion, the third portion to volumetrically expand into the first portion, and the first portion to volumetrically expand through the opening to form an interconnect electrically coupling the first semiconductor die and the second semiconductor die at the contact pad.

2 . The method of claim 1 , wherein:
the second layer of dielectric material has an additional opening corresponding to the opening; the contact pad includes an additional reservoir of conductive material adjacent to the additional opening; and the method further includes heating the additional reservoir of conductive material effective to cause the additional reservoir of conductive material to volumetrically expand through the additional opening to form the interconnect electrically coupling the first semiconductor die and the second semiconductor die.

3 . The method of claim 1 , wherein a volume of the reservoir of conductive material is at least 10 times a volume of the opening.

4 . The method of claim 1 , wherein:
the first portion volumetrically expands in a first direction; and the second portion volumetrically expands in a second direction different than the first direction.

5 . The method of claim 1 , further comprising creating a bond between the first layer of dielectric material and the second layer of dielectric material to align the first opening and the contact pad.

6 . The method of claim 1 , wherein the second portion is disposed under a portion of the first layer of dielectric material that does not include the opening.

7 . A semiconductor device assembly, comprising:
a first semiconductor die including:
a first layer of dielectric material having an opening; and
a reservoir of conductive material having a first portion located adjacent to and extending through the opening, a second portion remote from the opening, and a third portion coupling the first portion and the second portion and having a size configured to permit volumetric expansion of the second portion through the third portion to displace some of the conductive material from the third portion into the first portion; and
a second semiconductor die including:
a second layer of dielectric material; and
a contact pad corresponding to the opening,
wherein the reservoir of conductive material and the contact pad are coupled through a metal-metal bond to form an interconnect at the opening, the interconnect coupling the first semiconductor die and the second semiconductor die.

8 . The semiconductor device assembly of claim 7 , wherein:
the second layer of dielectric material has an additional opening corresponding to the opening; the contact pad includes an additional reservoir of conductive material adjacent to and extending through the additional opening; and the reservoir of conductive material and the additional reservoir of conductive material couple through a metal-metal bond to form the interconnect at the opening and at the additional opening.

9 . The semiconductor device assembly of claim 7 , wherein the conductive material includes copper.

10 . The semiconductor device assembly of claim 7 , wherein the first semiconductor die further includes internal circuitry coupled with the reservoir of conductive material.

11 . The semiconductor device assembly of claim 10 , wherein the second portion couples with the internal circuitry only through the third portion.

12 . The semiconductor device assembly of claim 7 , wherein the first portion and the second portion are at least partially located at a same vertical layer of the first semiconductor die.

13 . The semiconductor device assembly of claim 7 , wherein the third portion comprises one or more conductive traces coupling the first portion and the second portion.

14 . The semiconductor device assembly of claim 7 , wherein the second portion is disposed under a portion of the first layer of dielectric material that does not include the opening.

15 . The semiconductor device assembly of claim 7 , wherein the first portion has a first size and the second portion has a second size smaller than the first size.

16 . The semiconductor device assembly of claim 7 , wherein the first portion and the opening have a same width.

17 . A semiconductor die, comprising:
a first layer of dielectric material having an opening; and a reservoir of conductive material configured to volumetrically expand through the opening to form an interconnect coupling the semiconductor die and an additional semiconductor die, the reservoir of conductive material including:
a first portion located adjacent to and extending through the opening;
a second portion remote from the opening; and
a third portion coupling the first portion and the second portion and having a size configured to permit volumetric expansion of the second portion through the third portion to displace some of the conductive material from the third portion into the first portion,
wherein the first portion is exposed at the opening and the second portion is disposed under a portion of the first layer of dielectric material that does not include the opening.

18 . The semiconductor die of claim 17 , further comprising internal circuitry coupled with the reservoir of conductive material.

19 . The semiconductor die of claim 18 , wherein the second portion couples with the internal circuitry only through the third portion.

20 . The semiconductor die of claim 17 , wherein the third portion comprises one or more conductive traces coupling the first portion and the second portion.

Assignees

• Micron Technology Inc

Inventors

• Kirby Kyle K
• Mcdaniel Terrence B

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W80/163

  using active alignment, e.g. detecting marks and correcting position · CPC title

• H10W72/90

  Bond pads, in general · CPC title