Stacked package structure including a chip disposed on a redistribution layer and a molding layer comprises a recess

Patent metadata

Field	Value
Publication number	US-12568864-B2
Application number	US-202318203668-A
Country	US
Kind code	B2
Filing date	May 31, 2023
Priority date	Oct 7, 2022
Publication date	Mar 3, 2026
Grant date	Mar 3, 2026

Abstract

A stacked package structure and a manufacturing method thereof are provided. The stacked package structure includes an upper redistribution layer, a first chip, and an upper molding layer. The first chip is disposed on the upper redistribution layer and is electrically connected to the upper redistribution layer. The upper molding layer is disposed on the first chip and the upper redistribution layer, and is configured to package the first chip. The upper molding layer includes a recess, the recess is recessed relative to a surface of the upper molding layer away from the upper redistribution layer, and the recess is circumferentially formed around a periphery of the upper molding layer.

First claim

What is claimed is:

1 . A stacked packaging structure, comprising:
an upper redistribution layer comprising a first surface and a second surface opposite to the first surface; a first chip disposed on the first surface of the upper redistribution layer and electrically connected to the upper redistribution layer; and an upper molding layer disposed on the first chip and the first surface of the upper redistribution layer, and configured to encapsulate the first chip, wherein the upper molding layer comprises a recess, the recess is recessed relative to a surface of the upper molding layer away from the upper redistribution layer, and the recess is formed around a periphery of the upper molding layer; wherein no additional elements are provided between the upper molding layer and the upper redistribution layer at a position corresponding to the recess.

2 . The stacked packaging structure according to claim 1 , wherein the surface of the upper molding layer away from the upper redistribution layer comprises at least a first stepped surface and a second stepped surface, and the first stepped surface is a bottom surface of the recess.

3 . The stacked packaging structure according to claim 2 , further comprising a lid, wherein the lid is disposed on the upper molding layer.

4 . The stacked packaging structure according to claim 3 , wherein the upper molding layer further comprises an opening, and the opening is configured to expose a non-active surface of the first chip; and
the stacked package structure further comprises a thermal interface material, the thermal interface material is disposed on the upper molding layer and covers the non-active surface of the first chip, and the thermal interface material is disposed between the lid and the upper molding layer.

5 . The stacked packaging structure according to claim 1 , further comprising an electromagnetic interference (EMI) shielding layer, wherein the EMI shielding layer covers the surface of the upper molding layer.

6 . The stacked packaging structure according to claim 5 , further comprising a lower molding layer and a lower redistribution layer, wherein the lower molding layer is disposed on the second surface of the upper redistribution layer, and the lower redistribution layer disposed on a surface of the lower molding layer away from the upper redistribution layer; and
wherein the EMI shielding layer further covers side surfaces of the upper molding layer, the upper redistribution layer, the lower molding layer, and the lower redistribution layer.

7 . The stacked packaging structure according to claim 1 , further comprising a second chip and a third chip, wherein the second chip and the third chip are disposed on the second surface of the upper redistribution layer and electrically connected to the upper redistribution layer, the second chip is laterally adjacent to the third chip, and the first chip is electrically connected to the third chip and the second chip through the upper redistribution layer.

8 . The stacked packaging structure according to claim 7 , further comprising a lower molding layer disposed on the second surface of the upper redistribution layer, and configured to encapsulate the second chip and the third chip, wherein material of the lower molding layer is different from material of the upper molding layer.

9 . The stacked packaging structure according to claim 8 , wherein a coefficient of thermal expansion of the material of the lower molding layer is different from a coefficient of thermal expansion of the material of the upper molding layer.

10 . The stacked packaging structure according to claim 8 , further comprising:
a lower redistribution layer disposed on a surface of the lower molding layer away from the upper redistribution layer; at least one conductive pillar electrically connected the upper redistribution layer and the lower redistribution layer; and a plurality of solder balls disposed on a surface of the lower redistribution layer away from the lower molding layer.

11 . The stacked packaging structure according to claim 10 , wherein an orthographic projection of the at least one conductive pillar on the lower redistribution layer overlaps with an orthographic projection of the first chip on the lower redistribution layer, and the first chip is electrically connected to the at least one conductive pillar through the upper redistribution layer.

Assignees

• Powertech Technology Inc

Inventors

• Tsai Pei-Chun
• Hsu Hung-Hsin
• Chang Chien Shang-Yu
• Lee Chia-Ling

Classifications

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W80/314

  characterized by direct bonding of pads or other interconnections · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title