Fan-out semiconductor package

Patent metadata

Field	Value
Publication number	US-11049782-B2
Application number	US-201916675805-A
Country	US
Kind code	B2
Filing date	Nov 6, 2019
Priority date	Nov 20, 2018
Publication date	Jun 29, 2021
Grant date	Jun 29, 2021

Abstract

A fan-out semiconductor package includes a frame including a plurality of wiring layers electrically connected to each other and having a recess portion having a bottom surface on which a stopper layer is disposed, a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, the inactive surface being disposed in the recess portion to face the stopper layer, an encapsulant covering at least a portion of the frame and at least a portion of the semiconductor chip, the encapsulant being disposed in at least a portion of the recess portion, and a connection structure disposed on the frame and the active surface and including a redistribution layer electrically connected to the plurality of wiring layers and the connection pad. A thickness of the stopper layer is greater than a thickness of each of the plurality of wiring layers.

First claim

What is claimed is:

1. A fan-out semiconductor package comprising:
a frame including a plurality of wiring layers electrically connected to each other, and having a recess portion having a bottom surface on which a stopper layer is disposed;
a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, the inactive surface being disposed in the recess portion to face the stopper layer;
an encapsulant covering at least a portion of the frame and at least a portion of the semiconductor chip, the encapsulant being disposed in at least a portion of the recess portion; and
a connection structure disposed on the frame and the active surface of the semiconductor chip, and including a redistribution layer electrically connected to the plurality of wiring layers and the connection pad,
wherein a thickness of the stopper layer is greater than a thickness of each of the plurality of wiring layers,
wherein the stopper layer comprises a plurality of metal layers that respectively comprise a metal material, and
wherein one of the plurality of metal layers is disposed on the same level as one of the plurality of wiring layers.

2. The fan-out semiconductor package of claim 1 , wherein at least one of the plurality of wiring layers comprises a ground pattern, and
the stopper layer is electrically connected to the ground pattern.

3. The fan-out semiconductor package of claim 1 , wherein the frame comprises a first insulating layer, a first wiring layer disposed on a lower surface of the first insulating layer, a second wiring layer disposed on an upper surface of the first insulating layer, a second insulating layer disposed on the lower surface of the first insulating layer to cover the first wiring layer, a third insulating layer disposed on the upper surface of the first insulating layer to cover the second wiring layer, a third wiring layer disposed on a lower surface of the second insulating layer, and a fourth wiring layer disposed on an upper surface of the third insulating layer, and
the plurality of wiring layers include the first to fourth wiring layers.

4. The fan-out semiconductor package of claim 3 , wherein a first region of the stopper layer is disposed on the lower surface of the first insulating layer to be covered by the second insulating layer, and
a second region of the stopper layer is disposed on an upper surface of the second insulating layer, in such a manner that an edge thereof is covered by the first insulating layer.

5. The fan-out semiconductor package of claim 4 , wherein the edge of the second region of the stopper layer, covered by the first insulating layer, has a step from a portion of the second region of the stopper layer, the step exposed to the recess portion.

6. The fan-out semiconductor package of claim 3 , wherein the third wiring layer is disposed on a level lower than the stopper layer, with reference to the inactive surface of the semiconductor chip.

7. The fan-out semiconductor package of claim 1 , further comprising:
a first connection member electrically connecting the connection pad to the redistribution layer; and
a second connection member electrically connecting the plurality of wiring layers to the redistribution layer,
wherein the encapsulant covers side surfaces of each of the first and second connection members.

8. The fan-out semiconductor package of claim 7 , wherein a surface of each of the first and second connection members in contact with the connection structure is coplanar with a surface of the encapsulant in contact with the connection structure.

9. The fan-out semiconductor package of claim 8 , wherein the connection structure comprises:
an insulating layer disposed on a coplanar surface of the first and second connection members and the encapsulant;
first and second connection vias passing through the insulating layer and in contact with the first and second connection members, respectively; and
the redistribution layer disposed on the insulating layer and electrically connected to the first and second connection members by the first and second connection vias, respectively.

10. The fan-out semiconductor package of claim 1 , wherein a side wall of the recess portion is inclined with respect to the stopper layer.

11. The fan-out semiconductor package of claim 1 , wherein the inactive surface of the semiconductor chip is attached to the stopper layer through an adhesive member.

12. A fan-out semiconductor package comprising:
a frame including a first insulating layer, a first wiring layer disposed on a lower surface of the first insulating layer, a second wiring layer disposed on an upper surface of the first insulating layer, a second insulating layer disposed on the lower surface of the first insulating layer to cover the first wiring layer, a third insulating layer disposed on the upper surface of the first insulating layer to cover the second wiring layer, a third wiring layer disposed on a lower surface of the second insulating layer, and a fourth wiring layer disposed on an upper surface of the third insulating layer, the first to fourth wiring layers being electrically connected to each other, the frame having a recess portion having a bottom surface on which a stopper layer is disposed;
a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, the inactive surface being disposed in the recess portion to face the stopper layer;
an encapsulant covering at least a portion of the frame and at least a portion of the semiconductor chip, the encapsulant being disposed in at least a portion of the recess portion; and
a connection structure disposed on the frame and the active surface of the semiconductor chip, and including a redistribution layer electrically connected to the first to fourth wiring layers and the connection pad,
wherein the stopper layer includes:
a first metal layer embedded in the second insulating layer and exposed to an upper surface of the second insulating layer; and
a second metal layer of which an edge is embedded in the first insulating layer, the second metal layer covering a portion of the first metal layer exposed to the upper surface of the second insulating layer.

13. The fan-out semiconductor package of claim 12 , wherein the stopper layer has a thickness greater than a thickness of each of the first to fourth wiring layers.

14. A fan-out semiconductor package comprising:
a frame including a plurality of insulating layers and a plurality of wiring layers respectively disposed on the plurality of insulating layers and electrically connected to each other, the frame having a recess portion having a bottom surface on which a stopper layer is disposed;
a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, the inactive surface being disposed in the recess portion to face the stopper layer;
an encapsulant covering at least a portion of the frame and at least a portion of the semiconductor chip, the encapsulant being disposed in at least a portion of the recess portion; and
a connection structure disposed on the frame and the active surface of the semiconductor chip, and including a redistribution layer electrically connected to the plurality of wiring layers and the connection pad,
wherein the stopper layer includes a first portion embedded in the plurality of insulating layers, and
a remaining portion of the stopper layer is arranged outside the plurality of insulating layers.

15.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Hanul
• Ko Younggwan

Classifications

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/69

  Insulating materials thereof · CPC title

• H10W70/68

  Shapes or dispositions thereof · CPC title