Chip scale semiconductor package having back side metal layer and raised front side pad and method of making the same

Patent metadata

Field	Value
Publication number	US-12568845-B2
Application number	US-202318236856-A
Country	US
Kind code	B2
Filing date	Aug 22, 2023
Priority date	Aug 22, 2023
Publication date	Mar 3, 2026
Grant date	Mar 3, 2026

Abstract

A chip scale semiconductor package comprises a silicon layer, a back side metal layer, and a plurality of front side pads. Each of the plurality of front side pads comprises a respective copper member and a respective solder member. A method comprises the steps of: providing a wafer; grinding the back side of the wafer forming a peripheral ring; applying a metallization process to a grinded surface; removing the peripheral ring; forming a front side seed layer; forming a front side photoresist layer; applying a photolithography process; applying a front side copper plating process; applying a front side solder plating process; stripping the front side photoresist layer; etching the front side seed layer; and applying a singulation process.

First claim

The invention claimed is:

1 . A method for fabricating a chip scale semiconductor package, the method comprising the steps of:
providing a wafer, the wafer comprising a front side and a back side opposite the front side; grinding the back side of the wafer forming a peripheral ring; applying a metallization process to a grinded surface; removing the peripheral ring; forming a front side seed layer; forming a front side photoresist layer; applying a photolithography process; applying a front side copper plating process; applying a front side solder plating process; stripping the front side photoresist layer; etching the front side seed layer; and applying a singulation process so as to separate the chip scale semiconductor package from other chip scale semiconductor packages.

2 . The method of claim 1 ,
wherein the step of forming the front side seed layer is after the step of removing the peripheral ring; and wherein the step of forming the front side photoresist layer is after the step of forming the front side seed layer.

3 . The method of claim 1 ,
wherein the step of forming the front side seed layer is before the step of front side photoresist layer; and wherein the step of forming the front side photoresist layer is before the step of grinding the back side of the wafer.

4 . The method of claim 1 , wherein the step of forming the front side seed layer is before the step of front side photoresist layer; and wherein the step of forming the front side photoresist layer is before the step of applying the photolithography process; wherein the step of applying the front side solder plating process is before the step of grinding the back side of the wafer.

5 . The method of claim 1 further comprising
after the step of removing the peripheral ring, forming a molding compound layer on a metal layer formed by the metallization process.

6 . The method of claim 1 , wherein the chip scale semiconductor package comprises
a silicon layer; a back side metal layer; and a plurality of front side pads; wherein each of the plurality of front side pads comprises
a respective copper member; and
a respective solder member; and
wherein a back surface of the respective solder member is directly attached to a front surface of the respective copper member.

7 . The method of claim 6 ,
wherein a thickness of the respective copper member of each of the plurality of front side pads is in a range from twenty-five microns to fifty microns; and wherein a thickness of the respective solder member of each of the plurality of front side pads is in a range from one micron to five microns.

8 . The method of claim 6 , wherein the chip scale semiconductor package is attached to a printed circuit board (PCB);
wherein additional respective solder directly contacts a sidewall of the respective copper member of each of the plurality of front side pads; and wherein the respective solder member of each of the plurality of front side pads directly contacts the PCB.

9 . A method for fabricating a chip scale semiconductor package, the method comprising the steps of:
providing a wafer, the wafer comprising a front side and a back side opposite the front side; forming a front side molding compound layer; grinding the back side of the wafer forming a peripheral ring; applying a metallization process to a grinded surface; removing the peripheral ring; applying a laser drill process; forming a front side seed layer; forming a front side photoresist layer; applying a photolithography process; applying a front side copper plating process; applying a front side solder plating process; stripping the front side photoresist layer; etching the front side seed layer; and applying a singulation process so as to separate the chip scale semiconductor package from other chip scale semiconductor packages.

10 . The method of claim 9 , further comprising
before the step of applying the laser drill process, forming a back side molding compound layer.

11 . The method of claim 9 , wherein the chip scale semiconductor package comprises
a silicon layer; a back side metal layer; and a plurality of front side pads; wherein each of the plurality of front side pads comprises
a respective copper member; and
a respective solder member; and
wherein a back surface of the respective solder member is directly attached to a front surface of the respective copper member.

12 . The method of claim 11 ,
wherein a thickness of the respective copper member of each of the plurality of front side pads is in a range from twenty-five microns to fifty microns; and wherein a thickness of the respective solder member of each of the plurality of front side pads is in a range from one micron to five microns.

Assignees

• Alpha & Omega Semiconductor Int Lp

Inventors

• Xue Yan Xun
• Bobde Madhur
• Wang Long-Ching
• Niu Zhiqiang
• Lv Lin

Classifications

• H10W72/30

  Die-attach connectors · CPC title

• H10W72/20 Primary

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

• H10D64/01326 Primary

  Aspects related to lithography, isolation or planarisation of the conductor · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title