Packaging device including bumps and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-12568829-B2
Application number	US-202318186284-A
Country	US
Kind code	B2
Filing date	Mar 20, 2023
Priority date	Sep 27, 2022
Publication date	Mar 3, 2026
Grant date	Mar 3, 2026

Abstract

A packaging device including bumps and a method of manufacturing the packaging device are presented. In the method of manufacturing a packaging device, a dielectric layer that covers a packaging base is formed and a lower layer is formed over a packaging base including first and second connecting pads. A plurality of dummy bumps that overlaps with the dielectric layer is formed. A sealing pattern that covers the dummy bumps, filling areas between the dummy bumps, is formed. A lower layer pattern in which the plurality of dummy bumps have been disposed is formed by removing portions of the lower layer that are exposed and do not overlap with the sealing pattern.

First claim

What is claimed is:

1 . A method of manufacturing a packaging device, comprising:
forming, on a packaging base including first and second connecting pads, a dielectric layer that covers the packaging base and exposes the first and second connecting pads; forming a lower layer that covers the dielectric layer and the first and second connecting pads; forming a plurality of dummy bumps that overlaps with the dielectric layer; forming a sealing pattern that fills areas between the dummy bumps; and forming a first lower layer pattern on which the plurality of dummy bumps have been disposed by removing portions of the lower layer that are exposed and do not overlap with the sealing pattern.

2 . The method of claim 1 , wherein:
connecting bumps that overlap with the first and second connecting pads, respectively, are formed while forming the dummy bumps, and as the first lower layer pattern is being formed, second lower layer patterns that are bonded to the connecting bumps, respectively, are formed.

3 . The method of claim 2 , wherein the sealing pattern is further extended to cover the dummy bumps and to provide an opening the connecting bumps and area between the connecting bumps.

4 . The method of claim 2 , wherein, while sealing the dummy bumps and the connecting bumps by covering the dummy bumps and the connecting bumps with the sealing pattern, the sealing pattern further provides openings between one of the dummy bumps and one of the connecting bumps and between the connecting bumps.

5 . The method of claim 2 , wherein the forming of the dummy bumps and the connecting bumps comprises:
forming a mask pattern comprising openings that expose a portion of the lower layer; and filling the openings with conductive substances, respectively.

6 . The method of claim 5 , further comprising removing the mask pattern before forming the sealing pattern.

7 . The method of claim 1 , wherein the first lower layer pattern is formed to interconnect the plurality of dummy bumps.

8 . The method of claim 1 , wherein the first lower layer pattern is formed to be bonded to the dielectric layer and electrically isolated from the first and second connecting pads.

9 . The method of claim 1 , wherein the lower layer comprises an under bump metallurgy (UBM) layer.

10 . The method of claim 1 , wherein the packaging base comprises a semiconductor substrate or a printed circuit board (PCB).

Assignees

• Sk Hynix Inc
• Sk Hynic Inc

Inventors

• Lee Jae Jun
• Kim Jong Yeon
• Kim Jong Hoon
• Yang Ju Heon
• Lee Mi Seon

Classifications

• H10W72/221

  Structures or relative sizes · CPC title

• H10W72/244

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

• H10W72/01255

  by using masks · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/20 Primary

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title