Interconnector and electronic apparatus including the same

Patent metadata

Field	Value
Publication number	US-12568813-B2
Application number	US-202218145490-A
Country	US
Kind code	B2
Filing date	Dec 22, 2022
Priority date	Dec 27, 2021
Publication date	Mar 3, 2026
Grant date	Mar 3, 2026

Abstract

Provided are an interconnector and an electronic apparatus including the interconnector. The interconnector includes: a metal layer; a dielectric layer surrounding at least a portion of the metal layer; and an interlayer disposed between the metal layer and the dielectric layer and including a ternary metal oxide.

First claim

What is claimed is:

1 . An interconnector comprising:
a dielectric layer with a trench; a metal layer in the trench of the dielectric layer so that a lower surface and both lateral surfaces of the metal layer are surrounded by the dielectric layer; and an interlayer between the metal layer and the dielectric layer in the trench and comprising a ternary metal oxide.

2 . The interconnector of claim 1 , wherein the ternary metal oxide comprises a crystal structure corresponding to that of delafossite.

3 . The interconnector of claim 1 , wherein the ternary metal oxide comprises an ABO 2 compound where A and B are metals.

4 . The interconnector of claim 3 , wherein A of the ternary metal oxide is any one of Pt, Pd, and Ag, and B of the ternary metal oxide is any one of Co, Cr, Ni, and Rh.

5 . The interconnector of claim 1 , wherein the ternary metal oxide comprises at least one of PtCoO 2 , PdCoO 2 , PdCrO 2 , PdRhO 2 , and AgNiO 2 .

6 . The interconnector of claim 1 , wherein the interlayer has a thickness of about 15 nm or less.

7 . The interconnector of claim 1 , wherein the metal layer has a thickness of about 5 nm to about 50 nm.

8 . The interconnector of claim 1 , wherein the metal layer has a width of about 50 nm or less.

9 . The interconnector of claim 1 , wherein the interlayer has a bulk resistivity of about 10 −5 Ωcm or less.

10 . The interconnector of claim 1 , wherein the interlayer has a resistivity of about 10 −4 Ωcm or less.

11 . The interconnector of claim 1 , wherein the interlayer comprises an element which is included in the dielectric layer and is not oxygen.

12 . The interconnector of claim 1 , wherein the dielectric layer comprises a first dielectric layer defining trench having a given depth,
the interlayer comprises a first interlayer on an inner wall of the trench, and the metal layer comprises a first metal layer that fills the trench.

13 . The interconnector of claim 1 , wherein the dielectric layer comprises a second dielectric layer defining a via hole,
the interlayer comprises a second interlayer on an inner wall of the via hole, and the metal layer comprises a second metal layer that fills the via hole.

14 . An electronic apparatus comprising:
a device layer comprising at least one of an active device, a capacitor, and a resistor; and the interconnector of claim 1 , which is connected to the device layer.

15 . The electronic apparatus of claim 14 , wherein the device layer comprises at least one of a memory device, a display device, and an integrated circuit device.

16 . A method of forming an interposed, comprising:
provisioning a porous, single-layer dielectric layer; forming a trench in the porous, single-layer dielectric layer; depositing a ternary metal oxide in a sidewall of the trench; and filling the trench with a metal, wherein the porous, single-layer dielectric layer surrounds a bottom of and side surfaces of the trench.

17 . The method of claim 16 , wherein the ternary metal oxide includes any one of Pt, Pd, and Ag, and B of the ternary metal oxide is any one of Co, Cr, Ni.

18 . The method of claim 16 , wherein the forming the trench includes performing a plasma etching process.

19 . The method of claim 16 , wherein the metal comprises at least one of Cu, Ag, Au, Al, Pt, Pd, Rh, Ir, and Ru.

20 . The method of claim 16 , further comprising:
performing a heat treatment process after filling the trench.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Youngseok
• Yang Eunji
• Kwon Junyoung

Classifications

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10P50/28

  of insulating materials · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• C01P2002/00

  Crystal-structural characteristics · CPC title