Multifilament resistive memory with insulation layers

Patent metadata

Field	Value
Publication number	US-12568776-B2
Application number	US-202217941574-A
Country	US
Kind code	B2
Filing date	Sep 9, 2022
Priority date	Sep 9, 2022
Publication date	Mar 3, 2026
Grant date	Mar 3, 2026

Abstract

A grain-boundary self-aligned resistive memory structure is provided enabling the closely-packed formation of multiple, oxide-based, ReRAM elements in parallel, each with its own compliance resistor. The structure is capable of forming multiple filaments, one per element, with the aim of reducing the variability in the composite ReRAM cell.

First claim

What is claimed is:

1 . A non-volatile memory (NVM) structure comprising:
a filament forming layer located on a first metal layer; a plurality of pillar structures located on, and in direct physical contact with, the filament forming layer, wherein each pillar structure of the plurality of pillar structures includes a vertical stack of a second metal pillar and a resistive pillar; a dielectric isolation structure located between each pillar structure of the plurality of pillar structures, wherein the dielectric isolation structure has a topmost surface that is coplanar with a topmost surface of each of the pillar structures; and a third metal layer located on top of, and in direct physical contact with, the plurality of pillar structures.

2 . The NVM structure of claim 1 , wherein the dielectric isolation structure has a lateral width from 0.5 nm to 5.0 nm.

3 . The NVM structure of claim 1 , wherein the dielectric isolation structure has a bottommost surface that is in direct physical contact with the filament forming layer.

4 . The NVM structure of claim 1 , further comprising at least one filament present in the filament forming layer.

5 . The NVM structure of claim 4 , wherein the at least one filament extends from a bottommost surface of the second metal pillar of one of the pillar structures to a topmost surface of the first metal layer.

6 . The NVM structure of claim 1 , wherein the filament forming layer is composed of a dielectric metal oxide having a dielectric constant of 4.0 or greater.

7 . The NVM structure of claim 1 , wherein the first metal layer, the second metal pillar and the third metal layer are composed of an electrically conductive material, and the resistive pillar is composed of a resistive material having a higher resistivity that the electrically conductive material.

8 . The NVM structure of claim 7 , wherein the electrically conductive material is TiN and the resistive material is TiON.

9 . The NVM structure of claim 1 , wherein the dielectric isolation structure is composed of a dielectric material having a dielectric constant of 4.0 or greater.

10 . A non-volatile memory (NVM) structure comprising:
a plurality of resistive random access memory (ReRAM) elements located between a first metal layer and a third metal layer, wherein each ReRAM element comprises a filament forming layer, a filament located in the filament forming layer, and a pillar structure comprising a vertical stack of a second metal pillar and a resistive pillar, wherein the pillar structure is located on, and is in direct physical contact with, the filament forming layer, and the resistive pillar is in direct physical contact with the third metal layer, and each ReRAM element is connected in parallel to the first metal layer and the third metal layer; and a dielectric isolation structure located laterally adjacent to the pillar structure, wherein the dielectric isolation structure has a topmost surface that is coplanar with a topmost surface of the pillar structure.

11 . The NVM structure of claim 10 , wherein the dielectric isolation structure has a lateral width from 0.5 nm to 5.0 nm.

12 . The NVM structure of claim 10 , wherein the dielectric isolation structure has a bottommost surface that is in direct physical contact with the filament forming layer.

Assignees

• IBM

Inventors

• Solomon Paul Michael
• Ando Takashi
• Cartier Eduard Albert
• Rozen John

Classifications

• H10N70/063

  by etching of pre-deposited switching material layers, e.g. lithography · CPC title

• H10N70/028

  by conversion of electrode material, e.g. oxidation · CPC title

• H10N70/026

  by physical vapor deposition, e.g. sputtering · CPC title

• H10B63/80

  Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays · CPC title

• H10N70/841

  Electrodes · CPC title