Integrated circuit

Patent metadata

Field	Value
Publication number	US-12568685-B2
Application number	US-202318331011-A
Country	US
Kind code	B2
Filing date	Jun 7, 2023
Priority date	Sep 18, 2020
Publication date	Mar 3, 2026
Grant date	Mar 3, 2026

Abstract

A method includes a first set of active areas extending in a first direction and separated from each other along a second direction in a cell; first and second gate s that cross the first set of active areas along the second direction, the first gate being shared by a first transistor of a first type and a second transistor of a second type and the second gate being shared by a third transistor of the first type and a fourth transistor of the second type; and a set of conductive lines arranged in three metal tracks in the cell and coupling at least one of terminals of the first to fourth transistors to another one of the terminals of the first to fourth transistor. The first transistor is turned off to electrically disconnect a source/drain terminal of the first transistor from a source/drain terminal of the fourth transistor.

First claim

What is claimed is:

1 . An integrated circuit, comprising:
a first set of active areas extending in a first direction and separated from each other along a second direction in a cell; a first gate and a second gate that cross the first set of active areas along the second direction, wherein the first gate is shared by a first transistor of a first type and a second transistor of a second type, and the second gate is shared by a third transistor of the first type and a fourth transistor of the second type; and a set of conductive lines arranged in three metal tracks in the cell and configured to couple at least one of terminals of the first to fourth transistors to another one of the terminals of the first to fourth transistor, wherein the set of conductive lines extend in the first direction and are separated from each other in the first direction by spaces, wherein the first transistor is turned off to electrically disconnect a source/drain terminal of the first transistor from a source/drain terminal of the fourth transistor.

2 . The integrated circuit of claim 1 , wherein the third transistor is turned on to connect a drain/source terminal of the second transistor to the source/drain terminal of the fourth transistor.

3 . The integrated circuit of claim 1 , wherein the set of conductive lines comprise:
a first pair of the conductive lines having first and second conductive lines that are coupled to the first and second gates respectively; a second pair of the conductive lines having third and fourth conductive lines that are coupled to a drain/source terminal of the third transistor and the source/drain terminal of the first transistor; and a third pair of the conductive lines having fifth and sixth conductive lines that are coupled to a drain/source terminal of the fourth transistor and a drain/source terminal of the second transistor, wherein a length of the first pair of the conductive lines is different from that of the second pair of the conductive lines.

4 . The integrated circuit of claim 3 , wherein the length of the first pair of the conductive lines is different from that of the third pair of the conductive lines.

5 . The integrated circuit of claim 3 , wherein the second and third pairs of the conductive lines are arranged on the opposite sides of the first pair of conductive lines along the second direction.

6 . The integrated circuit of claim 3 , further comprising:
a pair of power rails arranged on two boundaries of the cell, wherein the first to third pairs of the conductive lines and the pair of power rails are arranged in a first layer.

7 . The integrated circuit of claim 6 , wherein there are no other conductive lines, rather than the first to third pair of conductive lines, in the first layer in the cell and between the pair of power rails.

8 . The integrated circuit of claim 1 , further comprising:
a third gate and first and second conductive patterns, wherein the first conductive pattern corresponds to a drain/source terminal of the third transistor and the second conductive pattern is configured to receive a first supply voltage from a first power rail overlapping the first to third gates, wherein the third gate and the first and second conductive patterns are included in a structure operating as a first switch to transmit the first supply voltage to the integrated circuit.

9 . The integrated circuit of claim 8 , further comprising:
a fourth gate and third and fourth conductive patterns, wherein the third conductive pattern corresponds to a drain/source terminal of the fourth transistor and the fourth conductive pattern is configured to receive a second supply voltage, different from the first supply voltage, from a second power rail, the first and second power rails arranged on the opposite sides of the set of conductive lines.

10 . The integrated circuit of claim 9 , wherein the fourth gate and the third and fourth conductive patterns are included in a structure operating as a second switch to transmit the second supply voltage to the integrated circuit.

11 . An integrated circuit, comprising:
a transmission gate, comprising: first to fourth transistors each including a gate, wherein the gates of the first and second transistors are coupled together and the gates of the third and fourth transistors are coupled together; a first conductive pattern that extends in a first direction and corresponds to drain/source terminals of the first and third transistors; a first conductive line extending in a second direction to couple a source/drain terminal of the first transistor and arranged in a first metal track; and a second conductive line extending in the second direction to couple to a source/drain terminal of the fourth transistor and arranged in a second metal track, wherein the first transistor is configured to be turned off to electrically disconnect the first conductive pattern from the first conductive line.

12 . The integrated circuit of claim 11 , wherein the first transistor is further configured to be turned on to electrically connect the first conductive pattern to the second conductive line.

13 . The integrated circuit of claim 11 , further comprising:
third and fourth conductive lines interposed between the first and second conductive lines and arranged in a third metal track, wherein the first to third metal tracks are within two opposite boundary of a cell including the first to fourth transistors.

14 . The integrated circuit of claim 11 , further comprising:
a first power rail arranged interposed between the first and second conductive lines and configured to transmit a power supply voltage to the integrated circuit, wherein the gates of the first and second transistors and the gates of the third and fourth transistors cross the first power rail in a layout view.

15 . The integrated circuit of claim 14 , further comprising:
second and third power rails extending in the second direction, wherein the first power rail is interposed between the second and third power rails, wherein the first conductive line in the first metal track is between the first and second power rails, and the second conductive line in the second metal track is between the first and third power rails.

16 . The integrated circuit of claim 15 , further comprising:
a third conductive line that is coupled to a source/drain terminal of the second transistor and extends in the second direction to cross a second conductive pattern extending in the first direction, wherein the second transistor is configured to be turned off to electrically disconnect the third conductive line from the first conductive pattern.

17 . An integrated circuit, comprising:
a first gate extending in a first direction and corresponding to gates of first and second transistors; a second gate extending in the first direction and corresponding to gates of third and fourth transistors, wherein the first to fourth transistors are configured as a transmission gate; a first conductive line coupled between first terminals of the second and third transistors and extending in a second direction in a first metal track of a cell; and a second conductive line coupled to first terminals of the first and fourth transistors and extending in the second direction in a second metal track of the cell, wherein the second transistor is configured to electrically disconnect the first conductive line from the second conductive line.

18 . The integrated circuit of claim 17 , further comprising:
a conductive pattern dispose

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wu Guo-Huei
• Lu Chi-Yu
• Chen Ting-Yu
• Tien Li-Chun

Classifications

• H10D84/987

  Three levels of metal · CPC title

• H10D84/981

  Power supply lines · CPC title

• H10D84/975

  Wiring regions or routing · CPC title

• H10D84/966

  Gate electrode terminals or contacts · CPC title

• H10D84/961

  Substrate and well contacts · CPC title