Electronic devices and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-12568660-B2
Application number	US-202318309407-A
Country	US
Kind code	B2
Filing date	Apr 28, 2023
Priority date	Oct 22, 2019
Publication date	Mar 3, 2026
Grant date	Mar 3, 2026

Abstract

An electronic device includes a dielectric layer including crystal grains having aligned crystal orientations the dielectric layer may be between a substrate and a gate electrode. The dielectric layer may be between isolated first and second electrodes. A method of manufacturing an electronic device may include preparing a substrate having a channel layer, forming the dielectric layer on the channel layer, and forming a gate electrode on the dielectric layer.

First claim

What is claimed is:

1 . An electronic device, comprising:
a substrate; a ferroelectric layer on the substrate, the ferroelectric layer including crystal grains defined by grain boundaries; a gate electrode on the ferroelectric layer; a channel layer on the substrate or defined as a portion of the substrate, wherein the channel layer is overlapped with the gate electrode in a first direction that is perpendicular to a top surface of the substrate; a source and a drain on opposite sides of the channel layer in a second direction that is parallel to the top surface of the substrate; and a crystalline dielectric layer directly between the channel layer and the ferroelectric layer such that first opposite surfaces of the crystalline dielectric layer are each in direct contact with a separate layer of the channel layer or the ferroelectric layer, directly between the ferroelectric layer and the gate electrode such that second opposite surfaces of the crystalline dielectric layer are each in direct contact with a separate layer of the ferroelectric layer or the gate electrode, or combinations thereof, wherein the crystal grains of the ferroelectric layer have aligned crystal orientations substantially parallel to each other, wherein the crystalline dielectric layer includes crystal grains having crystal orientations that are different from the aligned crystal orientations of the crystal grains of the ferroelectric layer.

2 . The electronic device of claim 1 , wherein the channel layer includes at least one of Si, Ge, SiGe, Group III-V semiconductors, oxide semiconductors, nitride semiconductors, oxynitride semiconductors, 2D semiconductor materials, quantum dots, or organic semiconductors.

3 . The electronic device of claim 1 , wherein the ferroelectric layer includes an oxide of at least one of Hf, Si, Al, Zr, Y, La, Gd, or Sr.

4 . The electronic device of claim 3 , wherein the ferroelectric layer further includes a dopant.

5 . The electronic device of claim 1 , wherein the ferroelectric layer has a thickness, in the first direction that is perpendicular to the top surface of the substrate, of about 0.5 nm to about 4 nm.

6 . The electronic device of claim 1 , wherein the crystalline dielectric layer includes a 2D insulator material.

7 . An electronic device, comprising:
a substrate; a ferroelectric layer on the substrate, the ferroelectric layer including crystal grains defined by grain boundaries; a gate electrode on the ferroelectric layer; a channel layer on the substrate, wherein the channel layer is overlapped with the gate electrode in a first direction that is perpendicular to a top surface of the substrate; a source and a drain on opposite sides of the channel layer in a second direction that is parallel to the top surface of the substrate; and a crystalline dielectric layer directly between the channel layer and the ferroelectric layer such that first opposite surfaces of the crystalline dielectric layer are each in direct contact with a separate layer of the channel layer or the ferroelectric layer, directly between the ferroelectric layer and the gate electrode such that second opposite surfaces of the crystalline dielectric layer are each in direct contact with a separate layer of the ferroelectric layer or the gate electrode, or combinations thereof, wherein the crystal grains of the ferroelectric layer have <111> crystal orientations, and wherein the crystalline dielectric layer includes crystal grains having crystal orientations that are different from the <111> crystal orientations of the crystal grains of the ferroelectric layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jo Sanghyun
• Lee Eunha
• Heo Jinseong
• Kim Junghwa
• Lee Hyangsook
• Nam Seunggeol

Classifications

• H10W74/43

  comprising oxides, nitrides or carbides, e.g. ceramics or glasses · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D48/383

  Quantum effect devices, e.g. of devices using quantum reflection, diffraction or interference effects · CPC title

• H10P14/3466

  Crystal orientation · CPC title

• H10D30/797

  being in source or drain regions, e.g. SiGe source or drain · CPC title