Semiconductor device and manufacturing method of semiconductor device

Patent metadata

Field	Value
Publication number	US-12568625-B2
Application number	US-202318337232-A
Country	US
Kind code	B2
Filing date	Jun 19, 2023
Priority date	Feb 20, 2023
Publication date	Mar 3, 2026
Grant date	Mar 3, 2026

Abstract

A semiconductor device includes a gate structure including conductive layers and insulating layers that are alternately stacked. The semiconductor device also includes an insulating core located in the gate structure and including a long axis and a short axis. The semiconductor device further includes a first channel pattern and a second channel pattern surrounding the insulating core and located to face each other along the long axis. The semiconductor device additionally includes a barrier pattern surrounding the first channel pattern and the second channel pattern and having different thicknesses along the long axis and the short axis.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a gate structure including conductive layers and insulating layers that are alternately stacked; an insulating core located in the gate structure, the insulating core including a long axis and a short axis; a first channel pattern and a second channel pattern surrounding the insulating core and located to face each other along the long axis; and a barrier pattern surrounding the first channel pattern and the second channel pattern, the barrier pattern having different thicknesses at the long axis and the short axis.

2 . The semiconductor device of claim 1 , wherein each of the conductive layers includes a protrusion protruding toward the insulating core by passing through the barrier pattern between the first channel pattern and the second channel pattern.

3 . The semiconductor device of claim 2 , further comprising:
a liner surrounding the protrusion and extending between the barrier pattern and the conductive layers.

4 . The semiconductor device of claim 1 , wherein the barrier pattern includes first portions corresponding to the conductive layers and second portions corresponding to the insulating layers, and each of the second portions has a greater thickness at the long axis than at the short axis.

5 . The semiconductor device of claim 4 , wherein the second portions each have a greater thickness than the first portions.

6 . The semiconductor device of claim 1 , further comprising:
a memory pattern surrounding the first channel pattern and the second channel pattern, the memory pattern located between the first channel pattern and the barrier pattern and located between the second channel pattern and the barrier pattern.

7 . The semiconductor device of claim 6 , further comprising:
a liner surrounding the insulating core between the first channel pattern and the second channel pattern.

8 . The semiconductor device of claim 7 , wherein the memory pattern includes first portions corresponding to the conductive layers and second portions corresponding to the insulating layers, wherein the liner passes through the first portions, and wherein the second portions surround the liner.

9 . The semiconductor device of claim 1 , further comprising:
a liner surrounding the insulating core between the first channel pattern and the second channel pattern, the liner including first portions corresponding to the conductive layers and second portions corresponding to the insulating layers.

10 . The semiconductor device of claim 9 , wherein the first portions of the liner extend between the barrier pattern and the conductive layers.

11 . The semiconductor device of claim 9 , wherein the first portions of the liner surround the first channel pattern, the second channel pattern, and the barrier pattern.

12 . The semiconductor device of claim 9 , wherein the second portions of the liner are located between the insulating core and the barrier pattern.

13 . The semiconductor device of claim 1 , wherein the first channel pattern and the second channel pattern are separated from each other.

14 . A semiconductor device comprising:
a gate structure including conductive layers and insulating layers that are alternately stacked; a first channel pattern and a second channel pattern located in the gate structure; an insulating core located between the first channel pattern and the second channel pattern; a memory pattern surrounding the first channel pattern, the second channel pattern, and the insulating core; and a barrier pattern surrounding the memory pattern, wherein each of the conductive layers includes a protrusion protruding toward the insulating core through the barrier pattern and the memory pattern.

15 . The semiconductor device of claim 14 , further comprising:
a liner surrounding the insulating core between the first channel pattern and the second channel pattern.

16 . The semiconductor device of claim 15 , wherein the liner surrounds the protrusion and extends between the barrier pattern and the conductive layers.

17 . The semiconductor device of claim 15 , wherein the liner includes first portions corresponding to the conductive layers and second portions corresponding to the insulating layers, and wherein the second portion is located between the insulating core and the memory pattern.

Assignees

• Sk Hynix Inc

Inventors

• Choi Won Geun
• Kwak Rho Gyu
• Park In Su
• Jang Jung Shik
• Choi Jung Dal

Classifications

• H10B43/30 Primary

  characterised by the memory core region · CPC title

• H10B41/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B41/10

  characterised by the top-view layout · CPC title

• H10B41/30

  characterised by the memory core region · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title